/* Declarations for Intel 80386 opcode table
- Copyright 2007, 2008, 2009
+ Copyright 2007, 2008, 2009, 2010
Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
Cpu586,
/* i686 or better required */
Cpu686,
- /* CLFLUSH Instuction support required */
+ /* CLFLUSH Instruction support required */
CpuClflush,
- /* SYSCALL Instuctions support required */
+ /* NOP Instruction support required */
+ CpuNop,
+ /* SYSCALL Instructions support required */
CpuSYSCALL,
/* Floating point support required */
Cpu8087,
CpuAVX,
/* Intel L1OM support required */
CpuL1OM,
- /* Xsave/xrstor New Instuctions support required */
+ /* Xsave/xrstor New Instructions support required */
CpuXsave,
+ /* Xsaveopt New Instructions support required */
+ CpuXsaveopt,
/* AES support required */
CpuAES,
/* PCLMUL support required */
CpuXOP,
/* LWP support required */
CpuLWP,
- /* MOVBE Instuction support required */
+ /* MOVBE Instruction support required */
CpuMovbe,
/* EPT Instructions required */
CpuEPT,
- /* RDTSCP Instuction support required */
+ /* RDTSCP Instruction support required */
CpuRdtscp,
+ /* FSGSBASE Instructions required */
+ CpuFSGSBase,
+ /* RDRND Instructions required */
+ CpuRdRnd,
+ /* F16C Instructions required */
+ CpuF16C,
/* 64bit support available, used by -march= in assembler. */
CpuLM,
/* 64bit support required */
unsigned int cpui586:1;
unsigned int cpui686:1;
unsigned int cpuclflush:1;
+ unsigned int cpunop:1;
unsigned int cpusyscall:1;
unsigned int cpu8087:1;
unsigned int cpu287:1;
unsigned int cpuavx:1;
unsigned int cpul1om:1;
unsigned int cpuxsave:1;
+ unsigned int cpuxsaveopt:1;
unsigned int cpuaes:1;
unsigned int cpupclmul:1;
unsigned int cpufma:1;
unsigned int cpumovbe:1;
unsigned int cpuept:1;
unsigned int cpurdtscp:1;
+ unsigned int cpufsgsbase:1;
+ unsigned int cpurdrnd:1;
+ unsigned int cpuf16c:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
/* insn has VEX prefix:
1: 128bit VEX prefix.
2: 256bit VEX prefix.
+ 3: Scalar VEX prefix.
*/
-#define VEX128 1
-#define VEX256 2
+#define VEX128 1
+#define VEX256 2
+#define VEXScalar 3
Vex,
/* How to encode VEX.vvvv:
0: VEX.vvvv must be 1111b.
- 1: VEX.DNS. Register-only source is encoded in VEX.vvvv where
+ 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where
the content of source registers will be preserved.
VEX.DDS. The second register operand is encoded in VEX.vvvv
where the content of first source register will be overwritten
by the result.
- For assembler, there are no difference between VEX.DNS and
+ For assembler, there are no difference between VEX.NDS and
VEX.DDS.
2. VEX.NDD. Register destination is encoded in VEX.vvvv.
3. VEX.LWP. Register destination is encoded in VEX.vvvv and one
/* Any memory size. */
Anysize,
+ /* Vector 4 bit immediate. */
+ Vec_Imm4,
+
/* The last bitfield in i386_operand_type. */
OTMax
};
unsigned int ymmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
+ unsigned int vec_imm4:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif