#define CpuSSE4_2 (CpuSSE4_1 + 1)
/* SSE5 support required */
#define CpuSSE5 (CpuSSE4_2 + 1)
+/* AVX support required */
+#define CpuAVX (CpuSSE5 + 1)
/* Xsave/xrstor New Instuctions support required */
-#define CpuXsave (CpuSSE5 + 1)
+#define CpuXsave (CpuAVX + 1)
+/* AES support required */
+#define CpuAES (CpuXsave + 1)
+/* PCLMUL support required */
+#define CpuPCLMUL (CpuAES + 1)
+/* FMA support required */
+#define CpuFMA (CpuPCLMUL + 1)
+/* MOVBE Instuction support required */
+#define CpuMovbe (CpuFMA + 1)
+/* EPT Instructions required */
+#define CpuEPT (CpuMovbe + 1)
/* 64bit support available, used by -march= in assembler. */
-#define CpuLM (CpuXsave + 1)
+#define CpuLM (CpuEPT + 1)
/* 64bit support required */
#define Cpu64 (CpuLM + 1)
/* Not supported in the 64bit mode */
unsigned int cpusse4_1:1;
unsigned int cpusse4_2:1;
unsigned int cpusse5:1;
+ unsigned int cpuavx:1;
unsigned int cpuxsave:1;
+ unsigned int cpuaes:1;
+ unsigned int cpupclmul:1;
+ unsigned int cpufma:1;
+ unsigned int cpumovbe:1;
+ unsigned int cpuept:1;
unsigned int cpulm:1;
unsigned int cpu64:1;
unsigned int cpuno64:1;
#define RegKludge (IsString + 1)
/* The first operand must be xmm0 */
#define FirstXmm0 (RegKludge + 1)
+/* An implicit xmm0 as the first operand */
+#define Implicit1stXmm0 (FirstXmm0 + 1)
/* BYTE is OK in Intel syntax. */
-#define ByteOkIntel (FirstXmm0 + 1)
+#define ByteOkIntel (Implicit1stXmm0 + 1)
/* Convert to DWORD */
#define ToDword (ByteOkIntel + 1)
/* Convert to QWORD */
#define Drexv (Drex + 1)
/* special DREX for comparisons */
#define Drexc (Drexv + 1)
+/* insn has VEX prefix. */
+#define Vex (Drexc + 1)
+/* insn has 256bit VEX prefix. */
+#define Vex256 (Vex + 1)
+/* insn has VEX NDS. Register-only source is encoded in Vex
+ prefix. */
+#define VexNDS (Vex256 + 1)
+/* insn has VEX NDD. Register destination is encoded in Vex
+ prefix. */
+#define VexNDD (VexNDS + 1)
+/* insn has VEX W0. */
+#define VexW0 (VexNDD + 1)
+/* insn has VEX W1. */
+#define VexW1 (VexW0 + 1)
+/* insn has VEX 0x0F opcode prefix. */
+#define Vex0F (VexW1 + 1)
+/* insn has VEX 0x0F38 opcode prefix. */
+#define Vex0F38 (Vex0F + 1)
+/* insn has VEX 0x0F3A opcode prefix. */
+#define Vex0F3A (Vex0F38 + 1)
+/* insn has VEX prefix with 3 soures. */
+#define Vex3Sources (Vex0F3A + 1)
+/* instruction has VEX 8 bit imm */
+#define VexImmExt (Vex3Sources + 1)
+/* SSE to AVX support required */
+#define SSE2AVX (VexImmExt + 1)
+/* No AVX equivalent */
+#define NoAVX (SSE2AVX + 1)
/* Compatible with old (<= 2.8.1) versions of gcc */
-#define OldGcc (Drexc + 1)
+#define OldGcc (NoAVX + 1)
/* AT&T mnemonic. */
#define ATTMnemonic (OldGcc + 1)
/* AT&T syntax. */
unsigned int isstring:1;
unsigned int regkludge:1;
unsigned int firstxmm0:1;
+ unsigned int implicit1stxmm0:1;
unsigned int byteokintel:1;
unsigned int todword:1;
unsigned int toqword:1;
unsigned int drex:1;
unsigned int drexv:1;
unsigned int drexc:1;
+ unsigned int vex:1;
+ unsigned int vex256:1;
+ unsigned int vexnds:1;
+ unsigned int vexndd:1;
+ unsigned int vexw0:1;
+ unsigned int vexw1:1;
+ unsigned int vex0f:1;
+ unsigned int vex0f38:1;
+ unsigned int vex0f3a:1;
+ unsigned int vex3sources:1;
+ unsigned int veximmext:1;
+ unsigned int sse2avx:1;
+ unsigned int noavx:1;
unsigned int oldgcc:1;
unsigned int attmnemonic:1;
unsigned int attsyntax:1;
#define RegMMX (FloatReg + 1)
/* SSE register */
#define RegXMM (RegMMX + 1)
+/* AVX registers */
+#define RegYMM (RegXMM + 1)
/* Control register */
-#define Control (RegXMM + 1)
+#define Control (RegYMM + 1)
/* Debug register */
#define Debug (Control + 1)
/* Test register */
#define Tbyte (Qword + 1)
/* XMMWORD memory. */
#define Xmmword (Tbyte + 1)
+/* YMMWORD memory. */
+#define Ymmword (Xmmword + 1)
/* Unspecified memory size. */
-#define Unspecified (Xmmword + 1)
+#define Unspecified (Ymmword + 1)
/* Any memory size. */
#define Anysize (Unspecified + 1)
+/* VEX 4 bit immediate */
+#define Vex_Imm4 (Anysize + 1)
+
/* The last bitfield in i386_operand_type. */
-#define OTMax Anysize
+#define OTMax Vex_Imm4
#define OTNumOfUints \
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
unsigned int floatreg:1;
unsigned int regmmx:1;
unsigned int regxmm:1;
+ unsigned int regymm:1;
unsigned int control:1;
unsigned int debug:1;
unsigned int test:1;
unsigned int qword:1;
unsigned int tbyte:1;
unsigned int xmmword:1;
+ unsigned int ymmword:1;
unsigned int unspecified:1;
unsigned int anysize:1;
+ unsigned int vex_imm4:1;
#ifdef OTUnused
unsigned int unused:(OTNumOfBits - OTUnused);
#endif
{
char *reg_name;
i386_operand_type reg_type;
- unsigned int reg_flags;
+ unsigned char reg_flags;
#define RegRex 0x1 /* Extended register. */
#define RegRex64 0x2 /* Extended 8 bit register. */
- unsigned int reg_num;
-#define RegRip ((unsigned int ) ~0)
+ unsigned char reg_num;
+#define RegRip ((unsigned char ) ~0)
#define RegEip (RegRip - 1)
/* EIZ and RIZ are fake index registers. */
#define RegEiz (RegEip - 1)
#define RegRiz (RegEiz - 1)
+/* FLAT is a fake segment register (Intel mode). */
+#define RegFlat ((unsigned char) ~0)
+ signed char dw2_regnum[2];
+#define Dw2Inval (-1)
}
reg_entry;
projects / binutils-gdb.git / blobdiff