Add 0F to VEX opcode enums.

[binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 523d3900ad818d1bbf73b7702fe088991e936639..9442211f225d380cc7e78fdf0832101aec38d363 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -1,5 +1,5 @@
 /* Declarations for Intel 80386 opcode table
-   Copyright 2007, 2008, 2009
+   Copyright 2007, 2008, 2009, 2010
    Free Software Foundation, Inc.
 
    This file is part of the GNU opcodes library.
@@ -94,6 +94,8 @@ enum
   CpuL1OM,
   /* Xsave/xrstor New Instuctions support required */
   CpuXsave,
+  /* Xsaveopt New Instuctions support required */
+  CpuXsaveopt,
   /* AES support required */
   CpuAES,
   /* PCLMUL support required */
@@ -112,6 +114,12 @@ enum
   CpuEPT,
   /* RDTSCP Instuction support required */
   CpuRdtscp,
+  /* FSGSBASE Instructions required */
+  CpuFSGSBase,
+  /* RDRND Instructions required */
+  CpuRdRnd,
+  /* F16C Instructions required */
+  CpuF16C,
   /* 64bit support available, used by -march= in assembler.  */
   CpuLM,
   /* 64bit support required  */
@@ -168,6 +176,7 @@ typedef union i386_cpu_flags
       unsigned int cpuavx:1;
       unsigned int cpul1om:1;
       unsigned int cpuxsave:1;
+      unsigned int cpuxsaveopt:1;
       unsigned int cpuaes:1;
       unsigned int cpupclmul:1;
       unsigned int cpufma:1;
@@ -177,6 +186,9 @@ typedef union i386_cpu_flags
       unsigned int cpumovbe:1;
       unsigned int cpuept:1;
       unsigned int cpurdtscp:1;
+      unsigned int cpufsgsbase:1;
+      unsigned int cpurdrnd:1;
+      unsigned int cpuf16c:1;
       unsigned int cpulm:1;
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
@@ -271,18 +283,20 @@ enum
   /* insn has VEX prefix:
        1: 128bit VEX prefix.
        2: 256bit VEX prefix.
+       3: Scalar VEX prefix.
    */
-#define VEX128 1
-#define VEX256 2
+#define VEX128         1
+#define VEX256         2
+#define VEXScalar      3
   Vex,
   /* How to encode VEX.vvvv:
      0: VEX.vvvv must be 1111b.
-     1: VEX.DNS.  Register-only source is encoded in VEX.vvvv where
+     1: VEX.NDS.  Register-only source is encoded in VEX.vvvv where
        the content of source registers will be preserved.
        VEX.DDS.  The second register operand is encoded in VEX.vvvv 
        where the content of first source register will be overwritten
        by the result.
-       For assembler, there are no difference between VEX.DNS and
+       For assembler, there are no difference between VEX.NDS and
        VEX.DDS.
      2. VEX.NDD.  Register destination is encoded in VEX.vvvv.
      3. VEX.LWP.  Register destination is encoded in VEX.vvvv and one
@@ -498,6 +512,9 @@ enum
   /* Any memory size.  */
   Anysize,
 
+  /* Vector 4 bit immediate.  */
+  Vec_Imm4,
+
   /* The last bitfield in i386_operand_type.  */
   OTMax
 };
@@ -559,6 +576,7 @@ typedef union i386_operand_type
       unsigned int ymmword:1;
       unsigned int unspecified:1;
       unsigned int anysize:1;
+      unsigned int vec_imm4:1;
 #ifdef OTUnused
       unsigned int unused:(OTNumOfBits - OTUnused);
 #endif