x86: drop bogus IgnoreSize from SHA insns

[binutils-gdb.git] / opcodes / i386-opc.h

diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index e50097a6814b0d90e50be30a566e1ac373842230..a7f0ba2a9b4b7af8a2025a8a8aae900cdf2fda29 100644 (file)
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -43,6 +43,10 @@ enum
   Cpu586,
   /* i686 or better required */
   Cpu686,
+  /* CMOV Instruction support required */
+  CpuCMOV,
+  /* FXSR Instruction support required */
+  CpuFXSR,
   /* CLFLUSH Instruction support required */
   CpuClflush,
   /* NOP Instruction support required */
@@ -262,6 +266,8 @@ typedef union i386_cpu_flags
       unsigned int cpui486:1;
       unsigned int cpui586:1;
       unsigned int cpui686:1;
+      unsigned int cpucmov:1;
+      unsigned int cpufxsr:1;
       unsigned int cpuclflush:1;
       unsigned int cpunop:1;
       unsigned int cpusyscall:1;
@@ -549,11 +555,11 @@ enum
   EVex,
 
   /* AVX512 masking support:
-       1: Zeroing-masking.
+       1: Zeroing or merging masking depending on operands.
        2: Merging-masking.
        3: Both zeroing and merging masking.
    */
-#define ZEROING_MASKING 1
+#define DYNAMIC_MASKING 1
 #define MERGING_MASKING 2
 #define BOTH_MASKING    3
   Masking,
@@ -819,7 +825,6 @@ typedef union i386_operand_type
       unsigned int jumpabsolute:1;
       unsigned int esseg:1;
       unsigned int regmem:1;
-      unsigned int mem:1;
       unsigned int byte:1;
       unsigned int word:1;
       unsigned int dword:1;
@@ -856,6 +861,8 @@ typedef struct insn_template
                               unset if Regmem --> Reg. */
 #define Opcode_FloatR  0x8 /* Bit to swap src/dest for float insns. */
 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
+#define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */
+#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
 
   /* extension_opcode is the 3 bit extension for group <n> insns.
      This field is also used to store the 8-bit opcode suffix for the
@@ -896,11 +903,9 @@ typedef struct
 #define RegRex64    0x2  /* Extended 8 bit register.  */
 #define RegVRex            0x4  /* Extended vector register.  */
   unsigned char reg_num;
-#define RegRip ((unsigned char ) ~0)
-#define RegEip (RegRip - 1)
+#define RegIP  ((unsigned char ) ~0)
 /* EIZ and RIZ are fake index registers.  */
-#define RegEiz (RegEip - 1)
-#define RegRiz (RegEiz - 1)
+#define RegIZ  (RegIP - 1)
 /* FLAT is a fake segment register (Intel mode).  */
 #define RegFlat     ((unsigned char) ~0)
   signed char dw2_regnum[2];