opcodes/gas: blackfin: handle more ASTAT flags

[binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 12a8cbebff01c7f34f8c25053bb6f9aa079c1d2f..6dc615f38d7b81608754c804b8e1ac52971175c1 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,6 +1,6 @@
 /* mips-opc.c -- MIPS opcode list.
    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
-   2003, 2004, 2005, 2007, 2008, 2009  Free Software Foundation, Inc.
+   2003, 2004, 2005, 2006, 2007, 2008, 2009  Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -96,9 +96,6 @@
 #define I4_33   INSN_ISA4_32R2
 #define I5_33   INSN_ISA5_32R2
 
-/* MIPS16 ASE support.  */
-#define I16     INSN_MIPS16
-
 /* MIPS64 MIPS-3D ASE support.  */
 #define M3D     INSN_MIPS3D
 
@@ -188,8 +185,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,              I4_32|G3        },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,              I4_33   },
 {"nop",     "",         0x00000000, 0xffffffff, 0,                     INSN2_ALIAS,    I1      }, /* sll */
-{"ssnop",   "",         0x00000040, 0xffffffff, 0,                     INSN2_ALIAS,    I32|N55 }, /* sll */
-{"ehb",     "",         0x000000c0, 0xffffffff, 0,                     INSN2_ALIAS,    I33     }, /* sll */
+{"ssnop",   "",         0x00000040, 0xffffffff, 0,                     INSN2_ALIAS,    I1      }, /* sll */
+{"ehb",     "",         0x000000c0, 0xffffffff, 0,                     INSN2_ALIAS,    I1      }, /* sll */
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                  INSN2_ALIAS,    I1      }, /* addiu */
 {"li",     "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
 {"li",      "t,I",     0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
@@ -739,7 +736,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",     "a",       0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
-{"jalx",    "a",       0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
+{"jalx",    "a",       0x74000000, 0xfc000000, UBD|WR_31,              0,              I1      },
 {"la",      "t,A(b)",  0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
 {"lb",      "t,o(b)",  0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
 {"lb",      "t,A(b)",  0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
@@ -1338,6 +1335,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"syncs",   "",                0x0000018f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
 {"syncw",   "",                0x0000010f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
 {"syncws",  "",                0x0000014f, 0xffffffff, INSN_SYNC,              0,              IOCT    },
+{"sync_acquire", "",   0x0000044f, 0xffffffff, INSN_SYNC,              0,              I33     },
+{"sync_mb", "",                0x0000040f, 0xffffffff, INSN_SYNC,              0,              I33     },
+{"sync_release", "",   0x0000048f, 0xffffffff, INSN_SYNC,              0,              I33     },
+{"sync_rmb", "",       0x000004cf, 0xffffffff, INSN_SYNC,              0,              I33     },
+{"sync_wmb", "",       0x0000010f, 0xffffffff, INSN_SYNC,              0,              I33     },
 {"sync",    "",                0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
 {"sync",    "1",       0x0000000f, 0xfffff83f, INSN_SYNC,              0,              I32     },
 {"sync.p",  "",                0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
@@ -1506,12 +1508,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc2tl",   "N,p",     0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
 {"cfc2",    "t,G",     0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"ctc2",    "t,G",     0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
+{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
 {"dmfc2",   "t,G",     0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
 {"dmfc2",   "t,G,H",   0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
-{"dmfc2",   "t,i",     0x48200000, 0xffe00000, LCD|WR_t|RD_C2,         0,              IOCT    },
+{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"dmtc2",   "t,G",     0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
 {"dmtc2",   "t,G,H",   0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
-{"dmtc2",   "t,i",     0x48a00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              IOCT    },
 {"mfc2",    "t,G",     0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
 {"mfc2",    "t,G,H",   0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
 {"mfhc2",   "t,G",     0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },