sim: allow the environment configure option everywhere

[binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 7349ade30f9c4979996d16890a431d4a8d0f2f2e..79a8417760c49dd1752a9feee9710ac169514e5f 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2015 Free Software Foundation, Inc.
+   Copyright (C) 1993-2016 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -404,7 +404,7 @@ decode_mips_operand (const char *p)
 
    Because of the lookup algorithm used, entries with the same opcode
    name must be contiguous.
- 
+
    Many instructions are short hand for other instructions (i.e., The
    jal <register> instruction is short for jalr <register>).  */
 
@@ -425,9 +425,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li",                 "t,i",          0x34000000, 0xffe00000, WR_1,                   INSN2_ALIAS,    I1,             0,      0 }, /* ori */
 {"li",                 "t,I",          0,    (int) M_LI,       INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "d,s",          0,    (int) M_MOVE,     INSN_MACRO,             0,              I1,             0,      0 },
+{"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"move",               "d,s",          0x0000002d, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I3,             0,      0 },/* daddu */
 {"move",               "d,s",          0x00000021, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* addu */
-{"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"b",                  "p",            0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* beq 0,0 */
 {"b",                  "p",            0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* bgez 0 */
 {"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
@@ -2062,8 +2062,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"zcb",                        "(b)",          0x7000071f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 {"zcbt",               "(b)",          0x7000075f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 
-/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
-   mfhc0 and mthc0 XPA instructions, so they have been placed here 
+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
+   mfhc0 and mthc0 XPA instructions, so they have been placed here
    to allow the XPA instructions to take precedence.  */
 {"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 {"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
@@ -2110,7 +2110,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmtc2",              "t,+6",         0x48a00000, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
 {"qmtc2.i",            "t,+6",         0x48a00001, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
 {"qmtc2.ni",           "t,+6",         0x48a00000, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
+/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
    instructions, so they are here for the latters to take precedence.  */
 {"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE|I37 },
@@ -3010,8 +3010,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"copy_s.d",           "+k,+e+w",      0x78b80019, 0xfffe003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
 {"copy_u.b",           "+k,+e+o",      0x78c00019, 0xfff0003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"copy_u.h",           "+k,+e+u",      0x78e00019, 0xfff8003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"copy_u.w",           "+k,+e+v",      0x78f00019, 0xfffc003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"copy_u.d",           "+k,+e+w",      0x78f80019, 0xfffe003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
+{"copy_u.w",           "+k,+e+v",      0x78f00019, 0xfffc003f, WR_1|RD_2,              0,              0,              MSA64,  0 },
 {"insert.b",           "+d+o,d",       0x79000019, 0xfff0003f, MOD_1|RD_3,             0,              0,              MSA,    0 },
 {"insert.h",           "+d+u,d",       0x79200019, 0xfff8003f, MOD_1|RD_3,             0,              0,              MSA,    0 },
 {"insert.w",           "+d+v,d",       0x79300019, 0xfffc003f, MOD_1|RD_3,             0,              0,              MSA,    0 },