[aarch64] Remove argument pc from disas_aarch64_insn

[binutils-gdb.git] / opcodes / mips-opc.c

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index f43f9f5bbf31fba5d8182c79e22a5e89aee15bbb..b29a8ed4d0518947a5b88ef5406c6255d6d4f34a 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -48,11 +48,11 @@ decode_mips_operand (const char *p)
        case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
        case 's': SPECIAL (5, 21, NON_ZERO_REG);
        case 't': SPECIAL (5, 16, NON_ZERO_REG);
-       case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+       case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
        case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
        case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
        case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
-       case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+       case 'y': PREV_CHECK (5, 21, FALSE, TRUE, FALSE, FALSE);
        case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
        case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
        }
@@ -404,7 +404,7 @@ decode_mips_operand (const char *p)
 
    Because of the lookup algorithm used, entries with the same opcode
    name must be contiguous.
- 
+
    Many instructions are short hand for other instructions (i.e., The
    jal <register> instruction is short for jalr <register>).  */
 
@@ -425,9 +425,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li",                 "t,i",          0x34000000, 0xffe00000, WR_1,                   INSN2_ALIAS,    I1,             0,      0 }, /* ori */
 {"li",                 "t,I",          0,    (int) M_LI,       INSN_MACRO,             0,              I1,             0,      0 },
 {"move",               "d,s",          0,    (int) M_MOVE,     INSN_MACRO,             0,              I1,             0,      0 },
+{"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"move",               "d,s",          0x0000002d, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I3,             0,      0 },/* daddu */
 {"move",               "d,s",          0x00000021, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* addu */
-{"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"b",                  "p",            0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* beq 0,0 */
 {"b",                  "p",            0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* bgez 0 */
 {"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
@@ -1858,6 +1858,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.repa.qh",       "X,Y,Z",        0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.repb.qh",       "X,Y,Z",        0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.upsl.ob",       "X,Y,Z",        0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
+{"sigrie",             "u",            0x41700000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
 {"sle",                        "d,v,t",        0,    (int) M_SLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "d,v,I",        0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "S,T",          0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
@@ -2061,8 +2062,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"zcb",                        "(b)",          0x7000071f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 {"zcbt",               "(b)",          0x7000075f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 
-/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
-   mfhc0 and mthc0 XPA instructions, so they have been placed here 
+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the
+   mfhc0 and mthc0 XPA instructions, so they have been placed here
    to allow the XPA instructions to take precedence.  */
 {"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 {"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
@@ -2109,7 +2110,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmtc2",              "t,+6",         0x48a00000, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
 {"qmtc2.i",            "t,+6",         0x48a00001, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
 {"qmtc2.ni",           "t,+6",         0x48a00000, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
-/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
+/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
    instructions, so they are here for the latters to take precedence.  */
 {"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE|I37 },