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[binutils-gdb.git] / opcodes / mips16-opc.c

diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 233518535d0b83120bc3c46d28ec38bc2b65ff87..01cbcde489a64252ccc9edb221bc0dcf29d62be4 100644 (file)
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -1,5 +1,6 @@
 /* mips16-opc.c.  Mips16 opcode table.
-   Copyright 1996, 1997, 1998, 2000, 2005, 2007 Free Software Foundation, Inc.
+   Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007, 2012
+   Free Software Foundation, Inc.
    Contributed by Ian Lance Taylor, Cygnus Support
 
    This file is part of the GNU opcodes library.
@@ -19,8 +20,8 @@
    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
    MA 02110-1301, USA.  */
 
-#include <stdio.h>
 #include "sysdep.h"
+#include <stdio.h>
 #include "opcode/mips.h"
 
 /* This is the opcodes table for the mips16 processor.  The format of
@@ -32,7 +33,8 @@
    the opcodes table.  */
 
 #define UBD     INSN_UNCOND_BRANCH_DELAY
-#define BR      MIPS16_INSN_BRANCH
+#define UBR    MIPS16_INSN_UNCOND_BRANCH
+#define CBR    MIPS16_INSN_COND_BRANCH
 
 #define WR_x   MIPS16_INSN_WRITE_X
 #define WR_y   MIPS16_INSN_WRITE_Y
@@ -56,7 +58,8 @@
 #define RD_HI  INSN_READ_HI
 #define RD_LO  INSN_READ_LO
 
-#define TRAP   INSN_TRAP
+#define NODS   INSN_NO_DELAY_SLOT
+#define TRAP   INSN_NO_DELAY_SLOT
 
 #define I1     INSN_ISA1
 #define I3     INSN_ISA3
@@ -84,10 +87,10 @@ const struct mips_opcode mips16_opcodes[] =
 {"addu",    "x,P,V",   0x0800, 0xf800, WR_x|RD_PC,     0,      I1 },
 {"addu",    "x,S,V",   0x0000, 0xf800, WR_x|RD_SP,     0,      I1 },
 {"and",            "x,y",      0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0,      I1 },
-{"b",      "q",        0x1000, 0xf800, BR,             0,      I1 },
+{"b",      "q",        0x1000, 0xf800, UBR,            0,      I1 },
 {"beq",            "x,y,p",    0, (int) M_BEQ, INSN_MACRO,     0,      I1 },
 {"beq",     "x,U,p",   0, (int) M_BEQ_I, INSN_MACRO,   0,      I1 },
-{"beqz",    "x,p",     0x2000, 0xf800, BR|RD_x,        0,      I1 },
+{"beqz",    "x,p",     0x2000, 0xf800, CBR|RD_x,       0,      I1 },
 {"bge",            "x,y,p",    0, (int) M_BGE, INSN_MACRO,     0,      I1 },
 {"bge",     "x,8,p",   0, (int) M_BGE_I, INSN_MACRO,   0,      I1 },
 {"bgeu",    "x,y,p",   0, (int) M_BGEU, INSN_MACRO,    0,      I1 },
@@ -106,10 +109,10 @@ const struct mips_opcode mips16_opcodes[] =
 {"bltu",    "x,8,p",   0, (int) M_BLTU_I, INSN_MACRO,  0,      I1 },
 {"bne",            "x,y,p",    0, (int) M_BNE, INSN_MACRO,     0,      I1 },
 {"bne",     "x,U,p",   0, (int) M_BNE_I, INSN_MACRO,   0,      I1 },
-{"bnez",    "x,p",     0x2800, 0xf800, BR|RD_x,        0,      I1 },
+{"bnez",    "x,p",     0x2800, 0xf800, CBR|RD_x,       0,      I1 },
 {"break",   "6",       0xe805, 0xf81f, TRAP,           0,      I1 },
-{"bteqz",   "p",       0x6000, 0xff00, BR|RD_T,        0,      I1 },
-{"btnez",   "p",       0x6100, 0xff00, BR|RD_T,        0,      I1 },
+{"bteqz",   "p",       0x6000, 0xff00, CBR|RD_T,       0,      I1 },
+{"btnez",   "p",       0x6100, 0xff00, CBR|RD_T,       0,      I1 },
 {"cmpi",    "x,U",     0x7000, 0xf800, WR_T|RD_x,      0,      I1 },
 {"cmp",            "x,y",      0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0,      I1 },
 {"cmp",     "x,U",     0x7000, 0xf800, WR_T|RD_x,      0,      I1 },
@@ -169,6 +172,13 @@ const struct mips_opcode mips16_opcodes[] =
 {"jr",     "R",        0xe820, 0xffff, UBD|RD_31,      0,      I1 },
 {"j",      "x",        0xe800, 0xf8ff, UBD|RD_x,       0,      I1 },
 {"j",      "R",        0xe820, 0xffff, UBD|RD_31,      0,      I1 },
+/* MIPS16e compact branches.  We keep them near the ordinary branches
+   so that we easily find them when converting a normal branch to a
+   compact one.  */
+{"jalrc",   "x",       0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
+{"jalrc",   "R,x",     0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
+{"jrc",            "x",        0xe880, 0xf8ff, UBR|RD_x|NODS,  0,      I32 },
+{"jrc",            "R",        0xe8a0, 0xffff, UBR|RD_31|NODS, 0,      I32 },
 {"lb",     "y,5(x)",   0x8000, 0xf800, WR_y|RD_x,      0,      I1 },
 {"lbu",            "y,5(x)",   0xa000, 0xf800, WR_y|RD_x,      0,      I1 },
 {"ld",     "y,D(x)",   0x3800, 0xf800, WR_y|RD_x,      0,      I3 },
@@ -225,12 +235,8 @@ const struct mips_opcode mips16_opcodes[] =
 {"sw",     "R,V(S)",   0x6200, 0xff00, RD_31|RD_SP,    0,      I1 },
 {"xor",            "x,y",      0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0,      I1 },
   /* MIPS16e additions */
-{"jalrc",   "x",       0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
-{"jalrc",   "R,x",     0xe8c0, 0xf8ff, WR_31|RD_x|TRAP, 0,     I32 },
-{"jrc",     "x",       0xe880, 0xf8ff, RD_x|TRAP,      0,      I32 },
-{"jrc",     "R",       0xe8a0, 0xffff, RD_31|TRAP,     0,      I32 },
-{"restore", "M",       0x6400, 0xff80, WR_31|RD_SP|WR_SP|TRAP, 0,      I32 },
-{"save",    "m",       0x6480, 0xff80, RD_31|RD_SP|WR_SP|TRAP, 0,      I32 },
+{"restore", "M",       0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
+{"save",    "m",       0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
 {"sdbbp",   "6",       0xe801, 0xf81f, TRAP,           0,      I32 },
 {"seb",            "x",        0xe891, 0xf8ff, WR_x|RD_x,      0,      I32 },
 {"seh",            "x",        0xe8b1, 0xf8ff, WR_x|RD_x,      0,      I32 },