/* Disassemble MSP430 instructions.
- Copyright (C) 2002-2015 Free Software Foundation, Inc.
+ Copyright (C) 2002-2016 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
-
+
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
}
else if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
sprintf (op, "%d(r%d)", dst, regd);
}
}
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
sprintf (op, "#%d", dst);
if (dst > 9 || dst < 0)
sprintf (comm, "#0x%05x", dst);
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
}
else if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
sprintf (op, "%d(r%d)", dst, regd);
if (dst > 9 || dst < 0)
sprintf (comm, "%05x", dst);
Rm Register,
x(Rm) Indexed,
0xXXXX Relative,
- &0xXXXX Absolute
+ &0xXXXX Absolute
emulated_ins dst
basic_ins dst, dst. */
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
sprintf (op1, "0x%05x", dst & 0xfffff);
sprintf (comm1, "PC rel. 0x%05lx",
(long)((addr + 2 + dst) & 0xfffff));
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
}
else if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
cmd_len += 4;
*cycles = 6;
sprintf (op1, "%d(r%d)", dst, regd);
{
dst |= extended_src << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
sprintf (op1, "#%d", dst);
if (dst > 9 || dst < 0)
sprintf (comm1, "0x%05x", dst & 0xfffff);
{
dst |= extended_src << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
sprintf (op1, "0x%05x", dst & 0xfffff);
sprintf (comm1, "PC rel. 0x%05lx",
(long) ((addr + 2 + dst) & 0xfffff));
{
dst |= extended_src << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
}
else if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
sprintf (op1, "%d(r%d)", dst, regs);
if (dst > 9 || dst < -9)
sprintf (comm1, "0x%05x", dst);
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
sprintf (op2, "0x%05x", dst & 0xfffff);
sprintf (comm2, "PC rel. 0x%05lx",
(long)((addr + cmd_len + dst) & 0xfffff));
dst = msp430dis_opcode (addr + cmd_len, info);
cmd_len += 2;
if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
if (dst > 9 || dst < 0)
sprintf (comm2, "0x%04x", PS (dst));
if (extension_word)
{
dst |= extended_dst << 16;
if (dst & 0x80000)
- dst |= -1 << 20;
+ dst |= -1U << 20;
if (dst > 9 || dst < 0)
sprintf (comm2, "0x%05x", dst & 0xfffff);
}
dst = msp430dis_opcode (addr + 2, info);
cmd_len += 2;
if (dst & 0x8000)
- dst |= -1 << 16;
+ dst |= -1U << 16;
sprintf (op1, "%d(r%d)", dst, regs);
}
}
sprintf (comm1, "20-bit words");
bc =".a";
}
-
+
cycles = 2; /*FIXME*/
cmd_len = 2;
break;
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
-
+
case 1: /* MOVA @Rsrc+, Rdst */
cmd_len = 2;
if (strcmp (opcode->name, "reta") != 0)
sprintf (op2, "r%d", reg);
}
break;
-
+
case 2: /* MOVA &abs20, Rdst */
cmd_len = 4;
n <<= 16;
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
-
+
case 3: /* MOVA x(Rsrc), Rdst */
cmd_len = 4;
if (strcmp (opcode->name, "bra") != 0)
reg = n;
n = msp430dis_opcode (addr + 2, info);
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -1U << 16;
sprintf (op1, "%d(r%d)", n, reg);
if (n > 9 || n < 0)
{
sprintf (op1, "r%d", n);
n = msp430dis_opcode (addr + 2, info);
if (n & 0x8000)
- n |= -1 << 16;
+ n |= -1U << 16;
sprintf (op2, "%d(r%d)", n, reg);
if (n > 9 || n < 0)
{
sprintf (comm2, "0x%05x", n);
}
break;
-
+
case 8: /* MOVA #imm20, Rdst */
cmd_len = 4;
n <<= 16;
n |= msp430dis_opcode (addr + 2, info);
if (n & 0x80000)
- n |= -1 << 20;
+ n |= -1U << 20;
sprintf (op1, "#%d", n);
if (n > 9 || n < 0)
sprintf (comm1, "0x%05x", n);
if (strcmp (opcode->name, "bra") != 0)
sprintf (op2, "r%d", reg);
break;
-
+
case 12: /* MOVA Rsrc, Rdst */
cmd_len = 2;
sprintf (op1, "r%d", n);
}
else if (extension_word)
{
- if (extension_word & (1 << 6))
+ if (extension_word & BYTE_OPERATION)
bc = ".w";
else
{
sprintf (comm2, _("Reserved use of A/L and B/W bits detected"));
}
}
-
+
break;
case 1:
cmd_len +=
prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
}
- if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
+ /* Special case: RRC with an extension word and the ZC bit set is actually RRU. */
+ if (extension_word
+ && (extension_word & IGNORE_CARRY_BIT)
+ && strcmp (opcode->name, "rrc") == 0)
+ (*prin) (stream, "rrux%s", bc);
+ else if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
(*prin) (stream, "%sx%s", opcode->name, bc);
else
(*prin) (stream, "%s%s", opcode->name, bc);