opcodes/gas: blackfin: support OUTC debug insn

[binutils-gdb.git] / opcodes / ppc-opc.c

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index cfb47d169cabd45ed055e065c5392b07593e674e..972d3d9e2234dcf2436df57384d90b88a6adf138 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1908,8 +1908,9 @@ extract_dm (unsigned long insn,
 #define POWER6 PPC_OPCODE_POWER6
 #define POWER7 PPC_OPCODE_POWER7
 #define CELL   PPC_OPCODE_CELL
-#define PPC32  PPC_OPCODE_32 | PPC_OPCODE_PPC
-#define PPC64  PPC_OPCODE_64 | PPC_OPCODE_PPC
+#define PPC64  PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE
+#define NON32  (PPC_OPCODE_64 | PPC_OPCODE_POWER4 | PPC_OPCODE_PPCPS   \
+                | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN)
 #define PPC403 PPC_OPCODE_403
 #define PPC405 PPC_OPCODE_405
 #define PPC440 PPC_OPCODE_440
@@ -1925,15 +1926,13 @@ extract_dm (unsigned long insn,
 #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
 #define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
 #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON
-#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
 #define COM    PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
-#define COM32  PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
 #define M601   PPC_OPCODE_POWER | PPC_OPCODE_601
 #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
 #define MFDEC1 PPC_OPCODE_POWER
-#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
+#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE | PPC_OPCODE_TITAN
 #define BOOKE  PPC_OPCODE_BOOKE
-#define CLASSIC PPC_OPCODE_CLASSIC
+#define NO371  PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS
 #define PPCE300 PPC_OPCODE_E300
 #define PPCSPE PPC_OPCODE_SPE
 #define PPCISEL PPC_OPCODE_ISEL
@@ -2622,12 +2621,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cmplwi",     OPL(10,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, UI}},
 {"cmpldi",     OPL(10,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, UI}},
 {"cmpli",      OP(10),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, UI}},
-{"cmpli",      OP(10),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, UI}},
+{"cmpli",      OP(10),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, UI}},
 
 {"cmpwi",      OPL(11,0),      OPL_MASK,    PPCCOM,    PPCNONE,        {OBF, RA, SI}},
 {"cmpdi",      OPL(11,1),      OPL_MASK,    PPC64,     PPCNONE,        {OBF, RA, SI}},
 {"cmpi",       OP(11),         OP_MASK,     PPC,       PPCNONE,        {BF, L, RA, SI}},
-{"cmpi",       OP(11),         OP_MASK,     PWRCOM,    PPCNONE,        {BF, RA, SI}},
+{"cmpi",       OP(11),         OP_MASK,     PWRCOM,    PPC,            {BF, RA, SI}},
 
 {"addic",      OP(12),         OP_MASK,     PPCCOM,    PPCNONE,        {RT, RA, SI}},
 {"ai",         OP(12),         OP_MASK,     PWRCOM,    PPCNONE,        {RT, RA, SI}},
@@ -3429,7 +3428,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cmpw",       XOPL(31,0,0),   XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
 {"cmpd",       XOPL(31,0,1),   XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
 {"cmp",                X(31,0),        XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
-{"cmp",                X(31,0),        XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
+{"cmp",                X(31,0),        XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
 
 {"twlgt",      XTO(31,4,TOLGT), XTO_MASK,   PPCCOM,    PPCNONE,        {RA, RB}},
 {"tlgt",       XTO(31,4,TOLGT), XTO_MASK,   PWRCOM,    PPCNONE,        {RA, RB}},
@@ -3530,7 +3529,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"cmplw",      XOPL(31,32,0),  XCMPL_MASK,  PPCCOM,    PPCNONE,        {OBF, RA, RB}},
 {"cmpld",      XOPL(31,32,1),  XCMPL_MASK,  PPC64,     PPCNONE,        {OBF, RA, RB}},
 {"cmpl",       X(31,32),       XCMP_MASK,   PPC,       PPCNONE,        {BF, L, RA, RB}},
-{"cmpl",       X(31,32),       XCMPL_MASK,  PWRCOM,    PPCNONE,        {BF, RA, RB}},
+{"cmpl",       X(31,32),       XCMPL_MASK,  PWRCOM,    PPC,            {BF, RA, RB}},
 
 {"lvsr",       X(31,38),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
 {"lvehx",      X(31,39),       X_MASK,      PPCVEC,    PPCNONE,        {VD, RA, RB}},
@@ -3726,7 +3725,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"msgsnd",     XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2, PPCNONE,   {RB}},
 
-{"mtsr",       X(31,210), XRB_MASK|(1<<20), COM32,     TITAN,          {SR, RS}},
+{"mtsr",       X(31,210), XRB_MASK|(1<<20), COM,       NON32,          {SR, RS}},
 
 {"eratwe",     X(31,211),      X_MASK,      PPCA2,     PPCNONE,        {RS, RA, WS}},
 
@@ -3769,8 +3768,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"icblce",     X(31,238),      X_MASK,      PPCCHLK,   E500MC|PPCA2,   {CT, RA, RB}},
 {"msgclr",     XRTRA(31,238,0,0),XRTRA_MASK,E500MC|PPCA2, PPCNONE,     {RB}},
-{"mtsrin",     X(31,242),      XRA_MASK,    PPC32,     TITAN,          {RS, RB}},
-{"mtsri",      X(31,242),      XRA_MASK,    POWER32,   PPCNONE,        {RS, RB}},
+{"mtsrin",     X(31,242),      XRA_MASK,    PPC,       NON32,          {RS, RB}},
+{"mtsri",      X(31,242),      XRA_MASK,    POWER,     NON32,          {RS, RB}},
 
 {"dcbtstt",    XRT(31,246,0x10), XRT_MASK,  POWER7,    PPCNONE,        {RA, RB}},
 {"dcbtst",     X(31,246),      X_MASK,      POWER4,    PPCNONE,        {RA, RB, CT}},
@@ -3893,7 +3892,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"mftid",      XSPR(31,339, 17), XSPR_MASK, POWER,     PPCNONE,        {RT}},
 {"mfdsisr",    XSPR(31,339, 18), XSPR_MASK, COM,       TITAN,          {RT}},
 {"mfdar",      XSPR(31,339, 19), XSPR_MASK, COM,       TITAN,          {RT}},
-{"mfdec",      XSPR(31,339, 22), XSPR_MASK, MFDEC2|TITAN, PPCNONE,     {RT}},
+{"mfdec",      XSPR(31,339, 22), XSPR_MASK, MFDEC2,    MFDEC1,         {RT}},
 {"mfsdr0",     XSPR(31,339, 24), XSPR_MASK, POWER,     PPCNONE,        {RT}},
 {"mfsdr1",     XSPR(31,339, 25), XSPR_MASK, COM,       TITAN,          {RT}},
 {"mfsrr0",     XSPR(31,339, 26), XSPR_MASK, COM,       PPCNONE,        {RT}},
@@ -4097,9 +4096,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"tlbia",      X(31,370),      0xffffffff,  PPC,       TITAN,          {0}},
 
-{"mftbl",      XSPR(31,371,268), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
-{"mftbu",      XSPR(31,371,269), XSPR_MASK, CLASSIC,   PPCNONE,        {RT}},
-{"mftb",       X(31,371),      X_MASK,  CLASSIC|PPCA2, POWER7,         {RT, TBR}},
+{"mftbl",      XSPR(31,371,268), XSPR_MASK, PPC,       NO371,          {RT}},
+{"mftbu",      XSPR(31,371,269), XSPR_MASK, PPC,       NO371,          {RT}},
+{"mftb",       X(31,371),      X_MASK,      PPC|PPCA2, NO371|POWER7,   {RT, TBR}},
 
 {"lwaux",      X(31,373),      X_MASK,      PPC64,     PPCNONE,        {RT, RAL, RB}},
 
@@ -4421,7 +4420,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"ldbrx",      X(31,532),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RT, RA0, RB}},
 
-{"lswx",       X(31,533),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
+{"lswx",       X(31,533),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RA0, RB}},
 {"lsx",                X(31,533),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
 {"lwbrx",      X(31,534),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, RB}},
@@ -4465,9 +4464,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"lxsdx",      X(31,588),      XX1_MASK,    PPCVSX,    PPCNONE,        {XT6, RA, RB}},
 
-{"mfsr",       X(31,595), XRB_MASK|(1<<20), COM32,     TITAN,          {RT, SR}},
+{"mfsr",       X(31,595), XRB_MASK|(1<<20), COM,       NON32,          {RT, SR}},
 
-{"lswi",       X(31,597),      X_MASK,      PPCCOM,    PPCNONE,        {RT, RA0, NB}},
+{"lswi",       X(31,597),      X_MASK,      PPCCOM,    E500|E500MC,    {RT, RA0, NB}},
 {"lsi",                X(31,597),      X_MASK,      PWRCOM,    PPCNONE,        {RT, RA0, NB}},
 
 {"lwsync",     XSYNC(31,598,1), 0xffffffff, PPC,       E500,           {0}},
@@ -4514,11 +4513,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addeo.",     XO(31,138,1,1), XO_MASK,     PPCCOM,    PPCNONE,        {RT, RA, RB}},
 {"aeo.",       XO(31,138,1,1), XO_MASK,     PWRCOM,    PPCNONE,        {RT, RA, RB}},
 
-{"mfsrin",     X(31,659),      XRA_MASK,    PPC32,     TITAN,          {RT, RB}},
+{"mfsrin",     X(31,659),      XRA_MASK,    PPC,       NON32,          {RT, RB}},
 
 {"stdbrx",     X(31,660),      X_MASK, CELL|POWER7|PPCA2, PPCNONE,     {RS, RA0, RB}},
 
-{"stswx",      X(31,661),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
+{"stswx",      X(31,661),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, RB}},
 {"stsx",       X(31,661),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, RB}},
 
 {"stwbrx",     X(31,662),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, RB}},
@@ -4560,7 +4559,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addzeo.",    XO(31,202,1,1), XORB_MASK,   PPCCOM,    PPCNONE,        {RT, RA}},
 {"azeo.",      XO(31,202,1,1), XORB_MASK,   PWRCOM,    PPCNONE,        {RT, RA}},
 
-{"stswi",      X(31,725),      X_MASK,      PPCCOM,    PPCNONE,        {RS, RA0, NB}},
+{"stswi",      X(31,725),      X_MASK,      PPCCOM,    E500|E500MC,    {RS, RA0, NB}},
 {"stsi",       X(31,725),      X_MASK,      PWRCOM,    PPCNONE,        {RS, RA0, NB}},
 
 {"sthcx.",     XRC(31,726,1),  X_MASK,      POWER7,    PPCNONE,        {RS, RA0, RB}},