Properly merge GNU_PROPERTY_X86_ISA_1_USED (x86_64).

[binutils-gdb.git] / opcodes / riscv-dis.c

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index d760d701d49a43eabeae1359794e508ce842c898..5b29d62a8c426454452557f8cddb213f5af9118f 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1,5 +1,5 @@
 /* RISC-V disassembler
-   Copyright (C) 2011-2017 Free Software Foundation, Inc.
+   Copyright (C) 2011-2018 Free Software Foundation, Inc.
 
    Contributed by Andrew Waterman (andrew@sifive.com).
    Based on MIPS target.
@@ -21,7 +21,7 @@
    see <http://www.gnu.org/licenses/>.  */
 
 #include "sysdep.h"
-#include "dis-asm.h"
+#include "disassemble.h"
 #include "libiberty.h"
 #include "opcode/riscv.h"
 #include "opintl.h"
@@ -64,8 +64,8 @@ parse_riscv_dis_option (const char *option)
     }
   else
     {
-      /* Invalid option.  */
-      fprintf (stderr, _("Unrecognized disassembler option: %s\n"), option);
+      /* xgettext:c-format */
+      opcodes_error_handler (_("unrecognized disassembler option: %s"), option);
     }
 }
 
@@ -101,7 +101,7 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset)
 {
   if (pd->hi_addr[base_reg] != (bfd_vma)-1)
     {
-      pd->print_addr = pd->hi_addr[base_reg] + offset;
+      pd->print_addr = (base_reg != 0 ? pd->hi_addr[base_reg] : 0) + offset;
       pd->hi_addr[base_reg] = -1;
     }
   else if (base_reg == X_GP && pd->gp != (bfd_vma)-1)
@@ -153,6 +153,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
            case 'i':
              print (info->stream, "%d", (int)EXTRACT_RVC_SIMM3 (l));
              break;
+           case 'o':
            case 'j':
              print (info->stream, "%d", (int)EXTRACT_RVC_IMM (l));
              break;
@@ -225,6 +226,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 
        case 'b':
        case 's':
+         if ((l & MASK_JALR) == MATCH_JALR)
+           maybe_print_address (pd, rs1, 0);
          print (info->stream, "%s", riscv_gpr_names[rs1]);
          break;
 
@@ -443,6 +446,32 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
              pd->print_addr = -1;
            }
 
+         /* Finish filling out insn_info fields.  */
+         switch (op->pinfo & INSN_TYPE)
+           {
+           case INSN_BRANCH:
+             info->insn_type = dis_branch;
+             break;
+           case INSN_CONDBRANCH:
+             info->insn_type = dis_condbranch;
+             break;
+           case INSN_JSR:
+             info->insn_type = dis_jsr;
+             break;
+           case INSN_DREF:
+             info->insn_type = dis_dref;
+             break;
+           default:
+             break;
+           }
+
+         if (op->pinfo & INSN_DATA_SIZE)
+           {
+             int size = ((op->pinfo & INSN_DATA_SIZE)
+                         >> INSN_DATA_SIZE_SHIFT);
+             info->data_size = 1 << (size - 1);
+           }
+
          return insnlen;
        }
     }
@@ -497,7 +526,7 @@ The following RISC-V-specific disassembler options are supported for use\n\
 with the -M switch (multiple options should be separated by commas):\n"));
 
   fprintf (stream, _("\n\
-  numeric       Print numeric reigster names, rather than ABI names.\n"));
+  numeric       Print numeric register names, rather than ABI names.\n"));
 
   fprintf (stream, _("\n\
   no-aliases    Disassemble only into canonical instructions, rather\n\