Fix disassembly of RX zero-offset register indirect instructions.

[binutils-gdb.git] / opcodes / rx-decode.opc

diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
index f9b0df43f223cec1c52bfbf09fa877e7fa88fe65..2409f7f52062f7818c075116100cc928f062aac0 100644 (file)
--- a/opcodes/rx-decode.opc
+++ b/opcodes/rx-decode.opc
@@ -49,7 +49,7 @@ static int bwl[] =
   RX_Byte,
   RX_Word,
   RX_Long,
-  0 /* Bogus instructions can have a size field set to 3.  */
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
 static int sbwl[] =
@@ -57,15 +57,15 @@ static int sbwl[] =
   RX_SByte,
   RX_SWord,
   RX_Long,
-  0 /* Bogus instructions can have a size field set to 3.  */
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
-static int ubwl[] =
+static int ubw[] =
 {
   RX_UByte,
   RX_UWord,
-  RX_Long,
-  0 /* Bogus instructions can have a size field set to 3.  */
+  RX_Bad_Size,/* Bogus instructions can have a size field set to 2.  */
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
 static int memex[] =
@@ -131,7 +131,7 @@ static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
 
 #define BWL(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
 #define sBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
-#define uBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz]
+#define uBW(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubw[sz]
 #define P(t, n)            rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
 
 #define F(f) store_flags(rx, f)
@@ -221,7 +221,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld)
       ld->rx->op[n].type = RX_Operand_Register;
       break;
     case 0:
-      ld->rx->op[n].type = RX_Operand_Indirect;
+      ld->rx->op[n].type = RX_Operand_Zero_Indirect;
       ld->rx->op[n].addend = 0;
       break;
     case 1:
@@ -338,7 +338,7 @@ rx_decode_opcode (unsigned long pc AU,
   ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 
 /** 1111 1110 11sz isrc bsrc rdst      movu%s  [%1, %2], %0 */
-  ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
+  ID(movbi); uBW(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 
 /** 1111 1101 0010 0p sz rdst rsrc     mov%s   %1, %0 */
   ID(mov); sBWL (sz); SR(rsrc); F_____;
@@ -349,13 +349,13 @@ rx_decode_opcode (unsigned long pc AU,
   OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 
 /** 1011 w dsp a src b dst     movu%s  %1, %0 */
-  ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
+  ID(mov); uBW(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
 
 /** 0101 1 s ss rsrc rdst      movu%s  %1, %0 */
-  ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____;
+  ID(mov); uBW(s); SD(ss, rsrc, s); DR(rdst); F_____;
 
 /** 1111 1101 0011 1p sz rsrc rdst     movu%s  %1, %0 */
-  ID(mov); uBWL (sz); DR(rdst); F_____;
+  ID(mov); uBW (sz); DR(rdst); F_____;
    OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 
 /*----------------------------------------------------------------------*/