[aarch64] Remove argument pc from disas_aarch64_insn

[binutils-gdb.git] / opcodes / rx-decode.opc

diff --git a/opcodes/rx-decode.opc b/opcodes/rx-decode.opc
index 8bf1f94ff6ccba867ce3ae4b31ec6eb609275016..7c641fa3ff0897ba57de87c93aa6ca9a725928e0 100644 (file)
--- a/opcodes/rx-decode.opc
+++ b/opcodes/rx-decode.opc
@@ -1,5 +1,5 @@
 /* -*- c -*- */
-/* Copyright (C) 2012-2014 Free Software Foundation, Inc.
+/* Copyright (C) 2012-2015 Free Software Foundation, Inc.
    Contributed by Red Hat.
    Written by DJ Delorie.
 
@@ -48,21 +48,24 @@ static int bwl[] =
 {
   RX_Byte,
   RX_Word,
-  RX_Long
+  RX_Long,
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
 static int sbwl[] =
 {
   RX_SByte,
   RX_SWord,
-  RX_Long
+  RX_Long,
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
-static int ubwl[] =
+static int ubw[] =
 {
   RX_UByte,
   RX_UWord,
-  RX_Long
+  RX_Bad_Size,/* Bogus instructions can have a size field set to 2.  */
+  RX_Bad_Size /* Bogus instructions can have a size field set to 3.  */
 };
 
 static int memex[] =
@@ -81,7 +84,7 @@ static int memex[] =
                        rx->op[n].size = s )
 
 /* This is for the BWL and BW bitfields.  */
-static int SCALE[] = { 1, 2, 4 };
+static int SCALE[] = { 1, 2, 4, 0 };
 /* This is for the prefix size enum.  */
 static int PSCALE[] = { 4, 1, 1, 1, 2, 2, 2, 3, 4 };
 
@@ -128,7 +131,7 @@ static int dsp3map[] = { 8, 9, 10, 3, 4, 5, 6, 7 };
 
 #define BWL(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = bwl[sz]
 #define sBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = sbwl[sz]
-#define uBWL(sz)    rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubwl[sz]
+#define uBW(sz)     rx->op[0].size = rx->op[1].size = rx->op[2].size = rx->size = ubw[sz]
 #define P(t, n)            rx->op[n].size = (t!=3) ? RX_UByte : RX_Long;
 
 #define F(f) store_flags(rx, f)
@@ -246,7 +249,7 @@ rx_disp (int n, int type, int reg, int size, LocalData * ld)
 #define xZ 2
 #define xC 1
 
-#define F_____ 
+#define F_____
 #define F___ZC rx->flags_0 = rx->flags_s = xZ|xC;
 #define F__SZ_ rx->flags_0 = rx->flags_s = xS|xZ;
 #define F__SZC rx->flags_0 = rx->flags_s = xS|xZ|xC;
@@ -335,7 +338,7 @@ rx_decode_opcode (unsigned long pc AU,
   ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 
 /** 1111 1110 11sz isrc bsrc rdst      movu%s  [%1, %2], %0 */
-  ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
+  ID(movbi); uBW(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____;
 
 /** 1111 1101 0010 0p sz rdst rsrc     mov%s   %1, %0 */
   ID(mov); sBWL (sz); SR(rsrc); F_____;
@@ -346,13 +349,13 @@ rx_decode_opcode (unsigned long pc AU,
   OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 
 /** 1011 w dsp a src b dst     movu%s  %1, %0 */
-  ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
+  ID(mov); uBW(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____;
 
 /** 0101 1 s ss rsrc rdst      movu%s  %1, %0 */
-  ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____;
+  ID(mov); uBW(s); SD(ss, rsrc, s); DR(rdst); F_____;
 
 /** 1111 1101 0011 1p sz rsrc rdst     movu%s  %1, %0 */
-  ID(mov); uBWL (sz); DR(rdst); F_____;
+  ID(mov); uBW (sz); DR(rdst); F_____;
    OP(1, p ? RX_Operand_Predec : RX_Operand_Postinc, rsrc, 0);
 
 /*----------------------------------------------------------------------*/
@@ -363,10 +366,10 @@ rx_decode_opcode (unsigned long pc AU,
 
 /** 0110 1110 dsta dstb                pushm   %1-%2 */
   ID(pushm); SR(dsta); S2R(dstb); F_____;
-  
+
 /** 0111 1110 1011 rdst                pop     %0 */
   ID(mov); OP(1, RX_Operand_Postinc, 0, 0); DR(rdst); F_____;
-  
+
 /** 0111 1110 10sz rsrc                push%s  %1 */
   ID(mov); BWL(sz); OP(0, RX_Operand_Predec, 0, 0); SR(rsrc); F_____;