unsigned operand_val)
{
xtensa_isa isa = xtensa_default_isa;
- int signed_operand_val;
+ int signed_operand_val, status;
+ bfd_byte litbuf[4];
if (show_raw_fields)
{
&operand_val, memaddr);
info->target = operand_val;
(*info->print_address_func) (info->target, info);
+ /* Also display value loaded by L32R (but not if reloc exists,
+ those tend to be wrong): */
+ if ((info->flags & INSN_HAS_RELOC) == 0
+ && !strcmp ("l32r", xtensa_opcode_name (isa, opc)))
+ status = (*info->read_memory_func) (operand_val, litbuf, 4, info);
+ else
+ status = -1;
+
+ if (status == 0)
+ {
+ unsigned literal = bfd_get_bits (litbuf, 32,
+ info->endian == BFD_ENDIAN_BIG);
+
+ (*info->fprintf_func) (info->stream, " (");
+ (*info->print_address_func) (literal, info);
+ (*info->fprintf_func) (info->stream, ")");
+ }
}
else
{
if (nslots > 1)
(*info->fprintf_func) (info->stream, "{ ");
+ info->insn_type = dis_nonbranch;
+ info->insn_info_valid = 1;
+
first_slot = 1;
for (n = 0; n < nslots; n++)
{
(*info->fprintf_func) (info->stream, "%s",
xtensa_opcode_name (isa, opc));
+ if (xtensa_opcode_is_branch (isa, opc))
+ info->insn_type = dis_condbranch;
+ else if (xtensa_opcode_is_jump (isa, opc))
+ info->insn_type = dis_branch;
+ else if (xtensa_opcode_is_call (isa, opc))
+ info->insn_type = dis_jsr;
+
/* Print the operands (if any). */
noperands = xtensa_opcode_num_operands (isa, opc);
first = 1;