(no commit message)

[libreriscv.git] / openpower / atomics.mdwn

diff --git a/openpower/atomics.mdwn b/openpower/atomics.mdwn
index f1698ddea9f6ae7388c5d7b8323a322b598f573e..bf1a055e0152d5e791cd94da9dc7a88950592036 100644 (file)
--- a/openpower/atomics.mdwn
+++ b/openpower/atomics.mdwn
@@ -1,11 +1,23 @@
 # Draft proposal for improved atomic operations for the Power ISA
 
+**NOTE THIS PROPOSAL IS NOT BEING SUBMITTED DUE TO
+DISCOVERY DURING INVESTIGATION THAT ATOMICS ARE DESIGNED
+FOR MASSIVE DISTRIBUTED CLUSTERS. SIGNIFICANT ADDITIONAL
+RESEARCH IS REQUIRED SO THIS PROPOSAL IS PUT ON HOLD
+UNTIL BUDGET IS AVAILABLE**
+
 Links:
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=236>
 * [OpenCAPI spec](http://opencapi.org/wp-content/uploads/2017/02/OpenCAPI-TL.WGsec_.V3p1.2017Jan27.pdf) p47-49 for AMO section
 * [RISC-V A](https://github.com/riscv/riscv-isa-manual/blob/master/src/a.tex)
 * [[atomics/discussion]]
+* <http://www.rdrop.com/~paulmck/scalability/paper/N2745r.2011.03.04a.html>
+
+TODO:
+
+* investigate Power ISA 3.1 p1077 eh hint
+
 
 # Motivation
 
@@ -124,31 +136,25 @@ release guaranteed ordering semantics as well as 8 and
 
 AT-Form (TODO)
 
-* lat. RT,RA,FC,ew
-* lataq. RT,RA,FC,ew
-* latrl. RT,RA,FC,ew
-* lataqrl. RT,RA,FC,ew
-* stat. RS,RA,FC,ew
-* stataq. RS,RA,FC,ew
-* statrl. RS,RA,FC,ew
-* stataqrl. RS,RA,FC,ew
+* lat. RT,RA,FC,aq,rl,ew
+* stat. RS,RA,FC,aq,rl,ew
 
 **DRAFT** EXT031 and XO, these are near to the existing
 atomic memory operations
 
-|0.5|6.10|11.15|16.20|21|22|23.24|25.30 |31|name       | Form       |
-|-- | -- | --- | --- |--|--|---- |------|--|-----------|------------|
-|31 | RT | RA  | FC  |lr|sc|ew   |000101|/ |lat[aq][rl]| TODO-Form  |
-|31 | RS | RA  | FC  |lr|sc|ew   |100101|/ |stat[aq][rl]| TODO-Form |
+|0.5|6.10|11.15|16.20|21|22|23.24|25.30 |31|name| Form       |
+|-- | -- | --- | --- |--|--|---- |------|--|----|------------|
+|31 | RT | RA  | FC  |lr|sc|ew   |000101|Rc|lat | TODO-Form  |
+|31 | RS | RA  | FC  |lr|sc|ew   |100101|/ |stat| TODO-Form |
 
 * `ew` specifies the memory operation width: 0/1/2/3 8/16/32/64
 * If the `aq` bit is set,
   then no later atomic memory operations can be observed
   to take place before the AMO in this or other cores.
-  (A Write-after-Read Memory Hazard is created)
+  (A global Write-after-Read Memory Hazard is created)
 * If the `rl` bit is set, then other cores will not observe the AMO before 
   memory accesses preceding the AMO.
-  (A Read-after-Write Memory Hazard is created)
+  (A global Read-after-Write Memory Hazard is created)
 * Setting both the `aq` and the `rl` bit makes the sequence
   sequentially consistent, meaning that
   it cannot be reordered with respect to earlier or later atomic