# Draft proposal for improved atomic operations for the Power ISA
+**NOTE THIS PROPOSAL IS NOT BEING SUBMITTED DUE TO
+DISCOVERY DURING INVESTIGATION THAT ATOMICS ARE DESIGNED
+FOR MASSIVE DISTRIBUTED CLUSTERS. SIGNIFICANT ADDITIONAL
+RESEARCH IS REQUIRED SO THIS PROPOSAL IS PUT ON HOLD
+UNTIL BUDGET IS AVAILABLE**
+
Links:
* <https://bugs.libre-soc.org/show_bug.cgi?id=236>
* [OpenCAPI spec](http://opencapi.org/wp-content/uploads/2017/02/OpenCAPI-TL.WGsec_.V3p1.2017Jan27.pdf) p47-49 for AMO section
* [RISC-V A](https://github.com/riscv/riscv-isa-manual/blob/master/src/a.tex)
* [[atomics/discussion]]
+* <http://www.rdrop.com/~paulmck/scalability/paper/N2745r.2011.03.04a.html>
+
+TODO:
+
+* investigate Power ISA 3.1 p1077 eh hint
+
# Motivation
These two instructions, `lat` and `stat`, are identical
to `lwat/ldat` and `stwat/stdat` except add acquire and
release guaranteed ordering semantics as well as 8 and
-16 bit memory widths as well.
+16 bit memory widths.
AT-Form (TODO)
-* lat RT,RA,FC,ew
-* lataq RT,RA,FC,ew
-* latrl RT,RA,FC,ew
-* lataqrl RT,RA,FC,ew
-* stat RT,RA,FC,ew
-* stataq RT,RA,FC,ew
-* statrl RT,RA,FC,ew
-* stataqrl RT,RA,FC,ew
+* lat. RT,RA,FC,aq,rl,ew
+* stat. RS,RA,FC,aq,rl,ew
**DRAFT** EXT031 and XO, these are near to the existing
atomic memory operations
-|0.5|6.10|11.15|16.20|21|22|23.24|25.30 |31|name | Form |
-|-- | -- | --- | --- |--|--|---- |------|--|-----------|------------|
-|31 | RT | RA | FC |lr|sc|ew |000101|/ |lat[aq][rl]| TODO-Form |
-|31 | RS | RA | FC |lr|sc|ew |100101|/ |stat[aq][rl]| TODO-Form |
+|0.5|6.10|11.15|16.20|21|22|23.24|25.30 |31|name| Form |
+|-- | -- | --- | --- |--|--|---- |------|--|----|------------|
+|31 | RT | RA | FC |lr|sc|ew |000101|Rc|lat | TODO-Form |
+|31 | RS | RA | FC |lr|sc|ew |100101|/ |stat| TODO-Form |
* `ew` specifies the memory operation width: 0/1/2/3 8/16/32/64
* If the `aq` bit is set,
then no later atomic memory operations can be observed
to take place before the AMO in this or other cores.
- (A Write-after-Read Memory Hazard is created)
+ (A global Write-after-Read Memory Hazard is created)
* If the `rl` bit is set, then other cores will not observe the AMO before
memory accesses preceding the AMO.
- (A Read-after-Write Memory Hazard is created)
+ (A global Read-after-Write Memory Hazard is created)
* Setting both the `aq` and the `rl` bit makes the sequence
sequentially consistent, meaning that
it cannot be reordered with respect to earlier or later atomic
read functions v3.1 book II section 4.5.1 p1071
- | 00000 | RT, RT+1 | mem(EA,s) | Fetch and Add |
- | 00001 | RT, RT+1 | mem(EA,s) | Fetch and XOR |
- | 00010 | RT, RT+1 | mem(EA,s) | Fetch and OR |
- | 00011 | RT, RT+1 | mem(EA,s) | Fetch and AND |
- | 00100 | RT, RT+1 | mem(EA,s) | Fetch and Maximum Unsigned |
- | 00101 | RT, RT+1 | mem(EA,s) | Fetch and Maximum Signed |
- | 00110 | RT, RT+1 | mem(EA,s) | Fetch and Minimum Unsigned |
- | 00111 | RT, RT+1 | mem(EA,s) | Fetch and Minimum Signed |
- | 01000 | RT, RT+1 | mem(EA,s) | Swap |
- | 10000 | RT, RT+1, RT+2 | mem(EA,s) | Compare and Swap Not Equal |
- | 11000 | RT | mem(EA,s) mem(EA+s, s) | Fetch and Increment Bounded |
- | 11001 | RT | mem(EA,s) mem(EA+s, s) | Fetch and Increment Equal |
- | 11100 | RT | mem(EA-s,s) mem(EA, s) | Fetch and Decrement Bounded |
+|opcode| regs | memory | description |
+|------|----------------|------------------------|-----------------------------|
+|00000 | RT, RT+1 | mem(EA,s) | Fetch and Add |
+|00001 | RT, RT+1 | mem(EA,s) | Fetch and XOR |
+|00010 | RT, RT+1 | mem(EA,s) | Fetch and OR |
+|00011 | RT, RT+1 | mem(EA,s) | Fetch and AND |
+|00100 | RT, RT+1 | mem(EA,s) | Fetch and Maximum Unsigned |
+|00101 | RT, RT+1 | mem(EA,s) | Fetch and Maximum Signed |
+|00110 | RT, RT+1 | mem(EA,s) | Fetch and Minimum Unsigned |
+|00111 | RT, RT+1 | mem(EA,s) | Fetch and Minimum Signed |
+|01000 | RT, RT+1 | mem(EA,s) | Swap |
+|10000 | RT, RT+1, RT+2 | mem(EA,s) | Compare and Swap Not Equal |
+|11000 | RT | mem(EA,s) mem(EA+s, s) | Fetch and Increment Bounded |
+|11001 | RT | mem(EA,s) mem(EA+s, s) | Fetch and Increment Equal |
+|11100 | RT | mem(EA-s,s) mem(EA, s) | Fetch and Decrement Bounded |
store functions
- | 00000 RS mem(EA,s) Store Add
- | 00001 RS mem(EA,s) Store XOR
- | 00010 RS mem(EA,s) Store OR
- | 00011 RS mem(EA,s) Store AND
- | 00100 RS mem(EA,s) Store Maximum Unsigned
- | 00101 RS mem(EA,s) Store Maximum Signed
- | 00110 RS mem(EA,s) Store Minimum Unsigned
- | 00111 RS mem(EA,s) Store Minimum Signed
- | 11000 RS mem(EA,s) Store Twin
-
-These functions are recognised as being part of the
+|opcode| regs | memory | description |
+|------|------|-----------|-----------------------------|
+|00000 | RS | mem(EA,s) | Store Add |
+|00001 | RS | mem(EA,s) | Store XOR |
+|00010 | RS | mem(EA,s) | Store OR |
+|00011 | RS | mem(EA,s) | Store AND |
+|00100 | RS | mem(EA,s) | Store Maximum Unsigned |
+|00101 | RS | mem(EA,s) | Store Maximum Signed |
+|00110 | RS | mem(EA,s) | Store Minimum Unsigned |
+|00111 | RS | mem(EA,s) | Store Minimum Signed |
+|11000 | RS | mem(EA,s) | Store Twin |
+
+These functions are also recognised as being part of the
OpenCAPI Specification.
projects / libreriscv.git / blobdiff