add "Pseudo-code" keyword due to ikiwiki bug

[libreriscv.git] / openpower / isa / fixedarith.mdwn

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index d18987b8657bef423f6758d246761f8c11d4d1cb..251aaa7016d909e954a477925415431178701174 100644 (file)
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -4,6 +4,8 @@ D-Form
 
 * addi RT,RA,SI
 
+Pseudo-code:
+
     if RA = 0 then RT <- EXTS(SI)
     else           RT <- (RA) + EXTS(SI)
 
@@ -12,11 +14,14 @@ Special Registers Altered:
     None
 
 # Add Immediate Shifted
+# Add Immediate Shifted
 
 D-Form
 
 * addis RT,RA,SI
 
+Pseudo-code:
+
     if RA = 0 then RT <- EXTS(SI || [0]*16)
     else           RT <- (RA) + EXTS(SI || [0]*16)
 
@@ -25,11 +30,14 @@ Special Registers Altered:
     None
 
 # Add PC Immediate Shifted
+# Add PC Immediate Shifted
 
 DX-Form
 
 * addpcis RT,D
 
+Pseudo-code:
+
     D <- d0||d1||d2
     RT <- NIA + EXTS(D || [0]*16)
 
@@ -38,6 +46,7 @@ Special Registers Altered:
     None
 
 # Add
+# Add
 
 XO-Form
 
@@ -46,6 +55,8 @@ XO-Form
 * addo RT,RA,RB (OE=1 Rc=0)
 * addo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA) + (RB)
 
 Special Registers Altered:
@@ -54,6 +65,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Subtract From
+# Subtract From
 
 XO-Form
 
@@ -62,6 +74,8 @@ XO-Form
 * subfo RT,RA,RB (OE=1 Rc=0)
 * subfo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + (RB) + 1
 
 Special Registers Altered:
@@ -70,11 +84,14 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Add Immediate Carrying
+# Add Immediate Carrying
 
 D-Form
 
 * addic RT,RA,SI
 
+Pseudo-code:
+
     RT <- (RA) + EXTS(SI)
 
 Special Registers Altered:
@@ -82,11 +99,14 @@ Special Registers Altered:
     CA CA32
 
 # Add Immediate Carrying and Record
+# Add Immediate Carrying and Record
 
 D-Form
 
 * addic. RT,RA,SI
 
+Pseudo-code:
+
     RT <- (RA) + EXTS(SI)
 
 Special Registers Altered:
@@ -94,11 +114,14 @@ Special Registers Altered:
     CR0 CA CA32
 
 # Subtract From Immediate Carrying
+# Subtract From Immediate Carrying
 
 D-Form
 
 * subfic RT,RA,SI
 
+Pseudo-code:
+
     RT <- ¬(RA) + EXTS(SI) + 1
 
 Special Registers Altered:
@@ -106,6 +129,7 @@ Special Registers Altered:
     CA CA32
 
 # Add Carrying
+# Add Carrying
 
 XO-Form
 
@@ -114,6 +138,8 @@ XO-Form
 * addco RT,RA,RB (OE=1 Rc=0)
 * addco.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA) + (RB)
 
 Special Registers Altered:
@@ -123,6 +149,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Subtract From Carrying
+# Subtract From Carrying
 
 XO-Form
 
@@ -131,6 +158,8 @@ XO-Form
 * subfco RT,RA,RB (OE=1 Rc=0)
 * subfco.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + (RB) + 1
 
 Special Registers Altered:
@@ -140,6 +169,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Add Extended
+# Add Extended
 
 XO-Form
 
@@ -148,6 +178,8 @@ XO-Form
 * addeo RT,RA,RB (OE=1 Rc=0)
 * addeo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA) + (RB) + CA
 
 Special Registers Altered:
@@ -157,6 +189,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Subtract From Extended
+# Subtract From Extended
 
 XO-Form
 
@@ -165,6 +198,8 @@ XO-Form
 * subfeo RT,RA,RB (OE=1 Rc=0)
 * subfeo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + (RB) + CA
 
 Special Registers Altered:
@@ -174,6 +209,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Add to Minus One Extended
+# Add to Minus One Extended
 
 XO-Form
 
@@ -182,6 +218,8 @@ XO-Form
 * addmeo RT,RA (OE=1 Rc=0)
 * addmeo.  RT,RA (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA) + CA - 1
 
 Special Registers Altered:
@@ -191,6 +229,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Subtract From Minus One Extended
+# Subtract From Minus One Extended
 
 XO-Form
 
@@ -199,6 +238,8 @@ XO-Form
 * subfmeo RT,RA (OE=1 Rc=0)
 * subfmeo.  RT,RA (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + CA - 1
 
 Special Registers Altered:
@@ -208,11 +249,14 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Add Extended using alternate carry bit
+# Add Extended using alternate carry bit
 
 Z23-Form
 
 * addex RT,RA,RB,CY
 
+Pseudo-code:
+
     if CY=0 then RT <- (RA) + (RB) + OV
 
 Special Registers Altered:
@@ -220,6 +264,7 @@ Special Registers Altered:
     OV OV32                (if CY=0 )
 
 # Subtract From Zero Extended
+# Subtract From Zero Extended
 
 XO-Form
 
@@ -228,6 +273,8 @@ XO-Form
 * subfzeo RT,RA (OE=1 Rc=0)
 * subfzeo.  RT,RA (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + CA
 
 Special Registers Altered:
@@ -237,6 +284,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Add to Zero Extended
+# Add to Zero Extended
 
 XO-Form
 
@@ -245,6 +293,8 @@ XO-Form
 * addzeo RT,RA (OE=1 Rc=0)
 * addzeo.  RT,RA (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA) + CA
 
 Special Registers Altered:
@@ -254,6 +304,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Negate
+# Negate
 
 XO-Form
 
@@ -262,6 +313,8 @@ XO-Form
 * nego RT,RA (OE=1 Rc=0)
 * nego.  RT,RA (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- ¬(RA) + 1
 
 Special Registers Altered:
@@ -270,11 +323,14 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Multiply Low Immediate
+# Multiply Low Immediate
 
 D-Form
 
 * mulli RT,RA,SI
 
+Pseudo-code:
+
     prod[0:127] <- (RA) * EXTS(SI)
     RT <- prod[64:127]
 
@@ -283,12 +339,15 @@ Special Registers Altered:
     None
 
 # Multiply High Word
+# Multiply High Word
 
 XO-Form
 
 * mulhw RT,RA,RB (Rc=0)
 * mulhw.  RT,RA,RB (Rc=1)
 
+Pseudo-code:
+
     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
     RT[32:63] <- prod[0:31]
     RT[0:31] <- undefined[0:31]
@@ -298,6 +357,7 @@ Special Registers Altered:
     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 
 # Multiply Low Word
+# Multiply Low Word
 
 XO-Form
 
@@ -306,6 +366,8 @@ XO-Form
 * mullwo RT,RA,RB (OE=1 Rc=0)
 * mullwo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     RT <- (RA)[32:63] * (RB)[32:63]
 
 Special Registers Altered:
@@ -314,12 +376,15 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Multiply High Word Unsigned
+# Multiply High Word Unsigned
 
 XO-Form
 
 * mulhwu RT,RA,RB (Rc=0)
 * mulhwu.  RT,RA,RB (Rc=1)
 
+Pseudo-code:
+
     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
     RT[32:63] <- prod[0:31]
     RT[0:31] <- undefined[0:31]
@@ -329,6 +394,7 @@ Special Registers Altered:
     CR0 (bits 0:2 undefined in 64-bit mode) (if Rc=1)
 
 # Divide Word
+# Divide Word
 
 XO-Form
 
@@ -337,6 +403,8 @@ XO-Form
 * divwo RT,RA,RB (OE=1 Rc=0)
 * divwo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:31] <-  (RA)[32:63]
     divisor[0:31] <- (RB) [32:63]
     if (((dividend = 0x8000_0000) &
@@ -355,6 +423,7 @@ Special Registers Altered:
     SO OV OV32                              (if OE=1)
 
 # Divide Word Unsigned
+# Divide Word Unsigned
 
 XO-Form
 
@@ -363,6 +432,8 @@ XO-Form
 * divwuo RT,RA,RB (OE=1 Rc=0)
 * divwuo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:31] <- (RA)[32:63]
     divisor[0:31] <- (RB)[32:63]
     if divisor != 0 then
@@ -379,6 +450,7 @@ Special Registers Altered:
     SO OV OV32                              (if OE=1)
 
 # Divide Word Extended
+# Divide Word Extended
 
 XO-Form
 
@@ -387,6 +459,8 @@ XO-Form
 * divweo RT,RA,RB (OE=1 Rc=0)
 * divweo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:63] <- (RA)[32:63] || [0]*32
     divisor[0:63] <- [0]*32 || (RB)[32:63]
     if (divisor = 0x0000_0000_0000_0000) then
@@ -408,6 +482,7 @@ Special Registers Altered:
     SO OV OV32                              (if OE=1)
 
 # Divide Word Extended Unsigned
+# Divide Word Extended Unsigned
 
 XO-Form
 
@@ -416,6 +491,8 @@ XO-Form
 * divweuo RT,RA,RB (OE=1 Rc=0)
 * divweuo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:63] <- (RA)[32:63] || [0]*32
     divisor[0:63] <- [0]*32 || (RB)[32:63]
     if (divisor = 0x0000_0000_0000_0000) then
@@ -437,11 +514,14 @@ Special Registers Altered:
     SO OV OV32                              (if OE=1)
 
 # Modulo Signed Word
+# Modulo Signed Word
 
 X-Form
 
 * modsw RT,RA,RB
 
+Pseudo-code:
+
     dividend[0:31] <- (RA)[32:63]
     divisor [0:31] <- (RB)[32:63]
     if (((dividend = 0x8000_0000) &
@@ -459,11 +539,14 @@ Special Registers Altered:
     None
 
 # Modulo Unsigned Word
+# Modulo Unsigned Word
 
 X-Form
 
 * moduw RT,RA,RB
 
+Pseudo-code:
+
     dividend[0:31] <- (RA) [32:63]
     divisor [0:31] <- (RB) [32:63]
     if divisor = 0x0000_0000 then
@@ -479,11 +562,14 @@ Special Registers Altered:
     None
 
 # Deliver A Random Number
+# Deliver A Random Number
 
 X-Form
 
 * darn RT,L
 
+Pseudo-code:
+
     RT <- random(L)
 
 Special Registers Altered:
@@ -491,6 +577,7 @@ Special Registers Altered:
     none
 
 # Multiply Low Doubleword
+# Multiply Low Doubleword
 
 XO-Form
 
@@ -499,6 +586,8 @@ XO-Form
 * mulldo RT,RA,RB (OE=1 Rc=0)
 * mulldo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     prod[0:127] <- (RA) * (RB)
     RT <- prod[64:127]
 
@@ -508,12 +597,15 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Multiply High Doubleword
+# Multiply High Doubleword
 
 XO-Form
 
 * mulhd RT,RA,RB (Rc=0)
 * mulhd.  RT,RA,RB (Rc=1)
 
+Pseudo-code:
+
     prod[0:127] <- (RA) *  (RB)
     RT <- prod[0:63]
 
@@ -522,12 +614,15 @@ Special Registers Altered:
     CR0                     (if Rc=1)
 
 # Multiply High Doubleword Unsigned
+# Multiply High Doubleword Unsigned
 
 XO-Form
 
 * mulhdu RT,RA,RB (Rc=0)
 * mulhdu.  RT,RA,RB (Rc=1)
 
+Pseudo-code:
+
     prod[0:127] <- (RA) *  (RB)
     RT <- prod[0:63]
 
@@ -536,11 +631,14 @@ Special Registers Altered:
     CR0                    (if Rc=1)
 
 # Multiply-Add High Doubleword VA-Form
+# Multiply-Add High Doubleword VA-Form
 
 VA-Form
 
 * maddhd RT,RA.RB,RC
 
+Pseudo-code:
+
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- prod + EXTS(RC)
     RT <- sum[0:63]
@@ -550,11 +648,14 @@ Special Registers Altered:
     None
 
 # Multiply-Add High Doubleword Unsigned
+# Multiply-Add High Doubleword Unsigned
 
 VA-Form
 
 * maddhdu RT,RA.RB,RC
 
+Pseudo-code:
+
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- prod + EXTZ(RC)
     RT <- sum[0:63]
@@ -564,11 +665,14 @@ Special Registers Altered:
     None
 
 # Multiply-Add Low Doubleword
+# Multiply-Add Low Doubleword
 
 VA-Form
 
 * maddld RT,RA.RB,RC
 
+Pseudo-code:
+
     prod[0:127] <- (RA) * (RB)
     sum[0:127] <- prod + EXTS(RC)
     RT <- sum[64:127]
@@ -578,6 +682,7 @@ Special Registers Altered:
     None
 
 # Divide Doubleword
+# Divide Doubleword
 
 XO-Form
 
@@ -586,6 +691,8 @@ XO-Form
 * divdo RT,RA,RB (OE=1 Rc=0)
 * divdo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:63] <- (RA)
     divisor[0:63] <- (RB)
     if (((dividend = 0x8000_0000_0000_0000) &
@@ -603,6 +710,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Divide Doubleword Unsigned
+# Divide Doubleword Unsigned
 
 XO-Form
 
@@ -611,6 +719,8 @@ XO-Form
 * divduo RT,RA,RB (OE=1 Rc=0)
 * divduo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:63] <- (RA)
     divisor[0:63] <- (RB)
     if (divisor = 0x0000_0000_0000_0000) then
@@ -626,6 +736,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Divide Doubleword Extended
+# Divide Doubleword Extended
 
 XO-Form
 
@@ -634,6 +745,8 @@ XO-Form
 * divdeo RT,RA,RB (OE=1 Rc=0)
 * divdeo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:127] <-  (RA) || [0]*64
     divisor[0:127] <- [0*64] || (RB)
     if divisor = [0]*128 then
@@ -654,6 +767,7 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Divide Doubleword Extended Unsigned
+# Divide Doubleword Extended Unsigned
 
 XO-Form
 
@@ -662,6 +776,8 @@ XO-Form
 * divdeuo RT,RA,RB (OE=1 Rc=0)
 * divdeuo.  RT,RA,RB (OE=1 Rc=1)
 
+Pseudo-code:
+
     dividend[0:127] <-  (RA) || [0]*64
     divisor[0:127] <- [0*64] || (RB)
     if divisor = [0]*128 then
@@ -682,11 +798,14 @@ Special Registers Altered:
     SO OV OV32             (if OE=1)
 
 # Modulo Signed Doubleword
+# Modulo Signed Doubleword
 
 X-Form
 
 * modsd RT,RA,RB
 
+Pseudo-code:
+
     dividend <- (RA)
     divisor  <- (RB)
     if (((dividend = 0x8000_0000_0000_0000) &
@@ -703,11 +822,14 @@ Special Registers Altered:
     None
 
 # Modulo Unsigned Doubleword
+# Modulo Unsigned Doubleword
 
 X-Form
 
 * modud RT,RA,RB
 
+Pseudo-code:
+
     dividend <- (RA)
     divisor  <- (RB)
     if (divisor = 0x0000_0000_0000_0000) then