whoops pseudocode for divwe / divde checking wrong half of result

[libreriscv.git] / openpower / isa / fixedarith.mdwn

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index a3d054aacfe34063807c9a4ad68d0ea38b6433a1..7a03aff4676c28c8d78e1aafa545cbeee4a783c9 100644 (file)
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -6,8 +6,7 @@ D-Form
 
 Pseudo-code:
 
-    if RA = 0 then RT <- EXTS(SI)
-    else           RT <- (RA) + EXTS(SI)
+    RT <- (RA|0) + EXTS(SI)
 
 Special Registers Altered:
 
@@ -21,8 +20,7 @@ D-Form
 
 Pseudo-code:
 
-    if RA = 0 then RT <- EXTS(SI || [0]*16)
-    else           RT <- (RA) + EXTS(SI || [0]*16)
+    RT <- (RA|0) + EXTS(SI || [0]*16)
 
 Special Registers Altered:
 
@@ -350,8 +348,8 @@ Pseudo-code:
 
     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
     RT <- prod
-    overflow <- ((prod[0:33] != 0x0_0000_0000) &
-                 (prod[0:33] != 0x1_ffff_ffff))
+    overflow <- ((prod[0:32] != [0]*33) &
+                 (prod[0:32] != [1]*33))
 
 Special Registers Altered:
 
@@ -446,8 +444,8 @@ Pseudo-code:
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        if (result[32:63] = 0) then
-            RT[32:63] <- result[0:31]
+        if (result[0:31] = 0) then
+            RT[32:63] <- result[32:63]
             RT[0:31] <- undefined[0:31]
             overflow <- 0
         else
@@ -478,7 +476,7 @@ Pseudo-code:
     else
         result <- dividend /  divisor
         if (RA) < (RB) then
-            RT[32:63] <- result[0:31]
+            RT[32:63] <- result[32:63]
             RT[0:31] <- undefined[0:31]
             overflow <- 0
         else
@@ -541,11 +539,11 @@ Special Registers Altered:
 
 X-Form
 
-* darn RT,L
+* darn RT,L3
 
 Pseudo-code:
 
-    RT <- random(L)
+    RT <- random(L3)
 
 Special Registers Altered:
 
@@ -564,8 +562,8 @@ Pseudo-code:
 
     prod[0:127] <- MULS((RA), (RB))
     RT <- prod[64:127]
-    overflow <- ((prod[0:65] != 0x0_0000_0000_0000_0000) &
-                 (prod[0:65] != 0x1_ffff_ffff_ffff_ffff))
+    overflow <- ((prod[0:64] != [0]*65) &
+                 (prod[0:64] != [1]*65))
 
 Special Registers Altered:
 
@@ -721,8 +719,8 @@ Pseudo-code:
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        if result[64:127] = 0x0000_0000_0000_0000 then
-            RT <- result[63:127]
+        if result[0:64] = 0x0000_0000_0000_0000 then
+            RT <- result[0:63]
             overflow <- 0
         else
             overflow <- 1
@@ -752,7 +750,7 @@ Pseudo-code:
     else
         result <- dividend /  divisor
         if (RA) < (RB) then
-            RT <- result[63:127]
+            RT <- result[0:63]
             overflow <- 0
         else
             overflow <- 1