fix modsw spec

[libreriscv.git] / openpower / isa / fixedarith.mdwn

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 5f556607eb591fd3ecae0b7e0671b866ade49599..ee817dfd7441405cafe0999743f6ec5498a00204 100644 (file)
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -6,8 +6,7 @@ D-Form
 
 Pseudo-code:
 
-    if RA = 0 then RT <- EXTS(SI)
-    else           RT <- (RA) + EXTS(SI)
+    RT <- (RA|0) + EXTS(SI)
 
 Special Registers Altered:
 
@@ -21,8 +20,7 @@ D-Form
 
 Pseudo-code:
 
-    if RA = 0 then RT <- EXTS(SI || [0]*16)
-    else           RT <- (RA) + EXTS(SI || [0]*16)
+    RT <- (RA|0) + EXTS(SI || [0]*16)
 
 Special Registers Altered:
 
@@ -350,8 +348,8 @@ Pseudo-code:
 
     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
     RT <- prod
-    overflow <- ((prod[0:32] != 0x0_0000_0000) &
-                 (prod[0:32] != 0x1_ffff_ffff))
+    overflow <- ((prod[0:32] != [0]*33) &
+                 (prod[0:32] != [1]*33))
 
 Special Registers Altered:
 
@@ -441,13 +439,14 @@ XO-Form
 Pseudo-code:
 
     dividend[0:63] <- (RA)[32:63] || [0]*32
-    divisor[0:63] <- [0]*32 || (RB)[32:63]
+    divisor[0:63] <- EXTS64((RB)[32:63])
     if (divisor = 0x0000_0000_0000_0000) then
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        if (result[32:63] = 0) then
-            RT[32:63] <- result[0:31]
+        result32[0:63] <- EXTS64(result[32:63])
+        if (result32 = result) then
+            RT[32:63] <- result[32:63]
             RT[0:31] <- undefined[0:31]
             overflow <- 0
         else
@@ -476,9 +475,9 @@ Pseudo-code:
     if (divisor = 0x0000_0000_0000_0000) then
         overflow <- 1
     else
-        result <- dividend /  divisor
-        if (RA) < (RB) then
-            RT[32:63] <- result[0:31]
+        result <- dividend / divisor
+        if RA[32:63] <u RB[32:63] then
+            RT[32:63] <- result[32:63]
             RT[0:31] <- undefined[0:31]
             overflow <- 0
         else
@@ -500,15 +499,14 @@ X-Form
 Pseudo-code:
 
     dividend[0:31] <- (RA)[32:63]
-    divisor [0:31] <- (RB)[32:63]
+    divisor[0:31] <- (RB)[32:63]
     if (((dividend = 0x8000_0000) &
          (divisor = 0xffff_ffff)) |
          (divisor = 0x0000_0000)) then
         RT[0:63] <- undefined[0:63]
         overflow <- 1
     else
-        RT[32:63] <- MODS(dividend, divisor)
-        RT[0:31] <- undefined[0:31]
+        RT[0:63] <- EXTS64(MODS(dividend, divisor))
         overflow <- 0
 
 Special Registers Altered:
@@ -541,11 +539,11 @@ Special Registers Altered:
 
 X-Form
 
-* darn RT,L
+* darn RT,L3
 
 Pseudo-code:
 
-    RT <- random(L)
+    RT <- random(L3)
 
 Special Registers Altered:
 
@@ -564,8 +562,8 @@ Pseudo-code:
 
     prod[0:127] <- MULS((RA), (RB))
     RT <- prod[64:127]
-    overflow <- ((prod[0:64] != 0x0_0000_0000_0000_0000) &
-                 (prod[0:64] != 0x1_ffff_ffff_ffff_ffff))
+    overflow <- ((prod[0:64] != [0]*65) &
+                 (prod[0:64] != [1]*65))
 
 Special Registers Altered:
 
@@ -716,13 +714,13 @@ XO-Form
 Pseudo-code:
 
     dividend[0:127] <-  (RA) || [0]*64
-    divisor[0:127] <- [0*64] || (RB)
+    divisor[0:127] <- [0]*64 || (RB)
     if divisor = [0]*128 then
         overflow <- 1
     else
         result <- DIVS(dividend, divisor)
-        if result[64:127] = 0x0000_0000_0000_0000 then
-            RT <- result[63:127]
+        if result[0:64] = 0x0000_0000_0000_0000 then
+            RT <- result[0:63]
             overflow <- 0
         else
             overflow <- 1
@@ -746,13 +744,13 @@ XO-Form
 Pseudo-code:
 
     dividend[0:127] <-  (RA) || [0]*64
-    divisor[0:127] <- [0*64] || (RB)
+    divisor[0:127] <- [0]*64 || (RB)
     if divisor = [0]*128 then
         overflow <- 1
     else
         result <- dividend /  divisor
         if (RA) < (RB) then
-            RT <- result[63:127]
+            RT <- result[0:63]
             overflow <- 0
         else
             overflow <- 1