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[libreriscv.git] / openpower / isa / fixedstore.mdwn

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 99392326c578848fceb3b96bbb37611737fb7a6f..1a8fe115219a593d026c1e2976796ef9907fef41 100644 (file)
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -1,144 +1,344 @@
-# Store Byte  
+# Store Byte
 
-stb RS,D(RA)
+D-Form
 
-    if RA = 0 then b <-  0
-    else           b <-  (RA)
+* stb RS,D(RA)
+
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + EXTS(D)
     MEM(EA, 1) <- (RS)[56:63]
 
-# Store Byte Indexed  
+Special Registers Altered:
+
+    None
+
+# Store Byte Indexed
 
-stbx RS,RA,RB
+X-Form
 
-    if RA = 0 then b <- 0
-    else           b <- (RA)
+* stbx RS,RA,RB
+
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + (RB)
     MEM(EA, 1) <- (RS)[56:63]
 
-# Store Byte with Update 
+Special Registers Altered:
+
+    None
 
-stbu RS,D(RA)
+# Store Byte with Update
+
+D-Form
+
+* stbu RS,D(RA)
+
+Pseudo-code:
 
     EA <- (RA) + EXTS(D)
     MEM(EA, 1) <- (RS)[56:63]
     RA <- EA
 
-# Store Byte with Update Indexed 
+Special Registers Altered:
+
+    None
+
+# Store Byte with Update Indexed
+
+X-Form
+
+* stbux RS,RA,RB
 
-stbux RS,RA,RB
+Pseudo-code:
 
     EA <- (RA) + (RB)
     MEM(EA, 1) <- (RS)[56:63]
     RA <- EA
-# Store Halfword 
 
-sth RS,D(RA)
+Special Registers Altered:
 
-    if RA = 0 then b <-  0
-    else           b <-  (RA)
+    None
+
+# Store Halfword
+
+D-Form
+
+* sth RS,D(RA)
+
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + EXTS(D)
     MEM(EA, 2) <- (RS)[48:63]
 
-# Store Halfword Indexed 
+Special Registers Altered:
+
+    None
+
+# Store Halfword Indexed
 
-sthx RS,RA,RB
+X-Form
 
-    if RA = 0 then b <- 0
-    else           b <- (RA)
+* sthx RS,RA,RB
+
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + (RB)
     MEM(EA, 2) <- (RS)[48:63]
 
+Special Registers Altered:
+
+    None
+
 # Store Halfword with Update
 
-sthu RS,D(RA)
+D-Form
+
+* sthu RS,D(RA)
+
+Pseudo-code:
 
     EA <- (RA) + EXTS(D)
     MEM(EA, 2) <- (RS)[48:63]
     RA <- EA
 
-# Store Halfword with Update Indexed 
- 
-sthux RS,RA,RB
+Special Registers Altered:
+
+    None
+
+# Store Halfword with Update Indexed
+
+X-Form
+
+* sthux RS,RA,RB
+
+Pseudo-code:
 
     EA <- (RA) + (RB)
     MEM(EA, 2) <- (RS)[48:63]
     RA <- EA
 
+Special Registers Altered:
+
+    None
+
 # Store Word
 
-stw RS,D(RA) 
+D-Form
 
-    if RA = 0 then b <-  0
-    else           b <-  (RA)
+* stw RS,D(RA)
+
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + EXTS(D)
     MEM(EA, 4) <- (RS)[32:63]
 
-# Store Word Indexed 
+Special Registers Altered:
+
+    None
+
+# Store Word Indexed
+
+X-Form
+
+* stwx RS,RA,RB
 
-stwx RS,RA,RB 
+Pseudo-code:
 
-    if RA = 0 then b <- 0
-    else           b <- (RA)
+    b <- (RA|0)
     EA <- b + (RB)
     MEM(EA, 4) <- (RS)[32:63]
 
-# Store Word with Update 
+Special Registers Altered:
 
-stwu RS,D(RA)
+    None
+
+# Store Word with Update
+
+D-Form
+
+* stwu RS,D(RA)
+
+Pseudo-code:
 
     EA <- (RA) + EXTS(D)
-    MEM(EA, 4) <- (RS) 32:63
+    MEM(EA, 4) <- (RS)[32:63]
     RA <- EA
 
-# Store Word with Update Indexed  
+Special Registers Altered:
+
+    None
+
+# Store Word with Update Indexed
 
-stwux RS,RA,RB 
+X-Form
+
+* stwux RS,RA,RB
+
+Pseudo-code:
 
     EA <- (RA) + (RB)
-    MEM(EA, 4) <- (RS) 32:63
+    MEM(EA, 4) <- (RS)[32:63]
     RA <- EA
 
-# Store Doubleword  
+Special Registers Altered:
+
+    None
+
+# Store Doubleword
+
+DS-Form
 
-std RS,DS(RA)
+* std RS,DS(RA)
 
-    if RA = 0 then b <-  0
-    else           b <-  (RA)
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + EXTS(DS || 0b00)
     MEM(EA, 8) <- (RS)
 
-# Store Doubleword Indexed 
+Special Registers Altered:
+
+    None
+
+# Store Doubleword Indexed
+
+X-Form
 
-stdx RS,RA,RB
+* stdx RS,RA,RB
 
-    if RA = 0 then b <- 0
-    else           b <- (RA)
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + (RB)
     MEM(EA, 8) <- (RS)
 
-# Store Doubleword with Update 
+Special Registers Altered:
+
+    None
+
+# Store Doubleword with Update
+
+DS-Form
+
+* stdu RS,DS(RA)
+
+Pseudo-code:
+
+    EA <- (RA) + EXTS(DS || 0b00)
+    MEM(EA, 8) <- (RS)
+    RA <- EA
+
+Special Registers Altered:
 
-stdu RS,DS(RA)
+    None
 
-EA <- (RA) + EXTS(DS || 0b00)
-MEM(EA, 8) <- (RS)
-RA <- EA
+# Store Doubleword with Update Indexed
 
-Store Doubleword with Update Indexed 
+X-Form
 
-stdux RS,RA,RB
+* stdux RS,RA,RB
+
+Pseudo-code:
 
     EA <- (RA) + (RB)
     MEM(EA, 8) <- (RS)
     RA <- EA
 
+Special Registers Altered:
+
+    None
+
 # Store Quadword
 
-stq RSp,DS(RA)
+DS-Form
+
+* stq RSp,DS(RA)
 
-    if RA = 0 then b <-  0
-    else           b <-  (RA)
+Pseudo-code:
+
+    b <- (RA|0)
     EA <- b + EXTS(DS || 0b00)
     MEM(EA, 16) <- RSp
 
+Special Registers Altered:
+
+    None
+
+# Store Halfword Byte-Reverse Indexed
+
+X-Form
+
+* sthbrx RS,RA,RB
+
+Pseudo-code:
+
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 2) <- (RS) [56:63] || (RS)[48:55]
+
+Special Registers Altered:
+
+    None
+
+# Store Word Byte-Reverse Indexed
+
+X-Form
+
+* stwbrx RS,RA,RB
+
+Pseudo-code:
+
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
+                   ||(RS)[32:39])
+
+Special Registers Altered:
+
+    None
+
+# Store Doubleword Byte-Reverse Indexed
+
+X-Form
+
+* stdbrx RS,RA,RB
+
+Pseudo-code:
+
+    b <- (RA|0)
+    EA <- b + (RB)
+    MEM(EA, 8) <- ((RS) [56:63] || (RS)[48:55]
+                    || (RS)[40:47] || (RS)[32:39]
+                    || (RS)[24:31] || (RS)[16:23]
+                    || (RS)[8:15]  || (RS)[0:7])
+
+Special Registers Altered:
+
+    None
+
+# Store Multiple Word
+
+D-Form
+
+* stmw RS,D(RA)
+
+Pseudo-code:
+
+    b <- (RA|0)
+    EA <- b + EXTS(D)
+    r <- RS
+    do while r <= 31
+        MEM(EA, 4) <- GPR(r)[32:63]
+        r <-  r + 1
+        EA <-  EA + 4
+
+Special Registers Altered:
+
+    None
+