sync_up: Updated my section

[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 9d7c7e68055c63a7488511b6fe5dbce87d574211..6fb84e902bccea66d1d97d27d49710d0d3f21f02 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -2,7 +2,9 @@
 
 <!-- this is a test comment -->
 
-ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
+the: CPU instructions, register set, memory model, etc, that describe
+the way a machine works.
 
 These pages contain (in a strict machine-readable subset of mdwn)
 the pseudo-code for all opcodes in the POWER v3.0B Public Spec
@@ -20,17 +22,49 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/sprset]]
 * [[isa/stringldst]]
 * [[isa/system]]
-* [[isa/simplev]]
 
 FP instructions: useful for testing <http://weitz.de/ieee/>
 
 * [[isa/fpload]]
 * [[isa/fpstore]]
 * [[isa/fpmove]]
+* [[isa/fparith]]
+* [[isa/fpcvt]]
+
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+* [[isa/bitmanip]]
+* [[isa/av]] - Audio/Video includes minmax, sum of absolute difference etc.
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+* [[isa/pifpload]]
+* [[isa/pifpstore]]
+
+Scalar "Post-Increment" Draft Load/Store with Shift
+
+* [[isa/pifixedloadshift]]
+* [[isa/pifixedstoreshift]]
+* [[isa/pifploadshift]]
+* [[isa/pifpstoreshift]]
+
+Part of the DRAFT Simple-V Specification:
+
+* [[isa/simplev]]
+
+A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
 
 # Pseudocode syntax
 
-The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/pseudo/parser.py;hb=HEAD>
+The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
 
 The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first).  Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not.  Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax.  Thus the following pseudocode: