bug 1034: update spec page on bin/tern lut2/lut3

[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index d1067448bd5fe2d93915c15fca8e4d979d61eb74..6fb84e902bccea66d1d97d27d49710d0d3f21f02 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -37,10 +37,24 @@ on Simple-V).
 Explanation of the rules for twin register targets
 (implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
 
-* [[isa/svfixedload]] DEPRECATED, do not use.
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]
 * [[isa/bitmanip]]
+* [[isa/av]] - Audio/Video includes minmax, sum of absolute difference etc.
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+* [[isa/pifpload]]
+* [[isa/pifpstore]]
+
+Scalar "Post-Increment" Draft Load/Store with Shift
+
+* [[isa/pifixedloadshift]]
+* [[isa/pifixedstoreshift]]
+* [[isa/pifploadshift]]
+* [[isa/pifpstoreshift]]
 
 Part of the DRAFT Simple-V Specification: