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-ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
+the: CPU instructions, register set, memory model, etc, that describe
+the way a machine works.
These pages contain (in a strict machine-readable subset of mdwn)
the pseudo-code for all opcodes in the POWER v3.0B Public Spec
* [[isa/sprset]]
* [[isa/stringldst]]
* [[isa/system]]
-* [[isa/simplev]]
FP instructions: useful for testing <http://weitz.de/ieee/>
* [[isa/fparith]]
* [[isa/fpcvt]]
-Variants only available under the [[sv/svp64]] namespace
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
-* [[isa/svfixedload]]
+* [[isa/svfixedarith]]
* [[isa/svfparith]]
+* [[isa/bitmanip]]
+* [[isa/av]] - Audio/Video includes minmax, sum of absolute difference etc.
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+* [[isa/pifpload]]
+* [[isa/pifpstore]]
+
+Scalar "Post-Increment" Draft Load/Store with Shift
+
+* [[isa/pifixedloadshift]]
+* [[isa/pifixedstoreshift]]
+* [[isa/pifploadshift]]
+* [[isa/pifpstoreshift]]
+
+Part of the DRAFT Simple-V Specification:
+
+* [[isa/simplev]]
+
+A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
# Pseudocode syntax
projects / libreriscv.git / blobdiff