add IIT Roorkee 2021 talk

[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index da056edc936b96940f7ebb67fc48982db363392d..da3bfea983210ceb980c5b04532eb8bbb0b93b28 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -1,5 +1,7 @@
 # ISA Pseudo-code 
 
+<!-- this is a test comment -->
+
 ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
 
 These pages contain (in a strict machine-readable subset of mdwn)
@@ -20,9 +22,22 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/system]]
 * [[isa/simplev]]
 
+FP instructions: useful for testing <http://weitz.de/ieee/>
+
+* [[isa/fpload]]
+* [[isa/fpstore]]
+* [[isa/fpmove]]
+* [[isa/fparith]]
+* [[isa/fpcvt]]
+
+Variants only available under the [[sv/svp64]] namespace
+
+* [[isa/svfixedload]]
+* [[isa/svfparith]]
+
 # Pseudocode syntax
 
-The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/pseudo/parser.py;hb=HEAD>
+The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
 
 The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first).  Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not.  Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax.  Thus the following pseudocode: