# ISA Pseudo-code
+<!-- this is a test comment -->
+
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+
These pages contain (in a strict machine-readable subset of mdwn)
the pseudo-code for all opcodes in the POWER v3.0B Public Spec
* [[isa/sprset]]
* [[isa/stringldst]]
* [[isa/system]]
+* [[isa/simplev]]
+
+FP instructions: useful for testing <http://weitz.de/ieee/>
+
+* [[isa/fpload]]
+* [[isa/fpstore]]
+* [[isa/fpmove]]
+* [[isa/fparith]]
+* [[isa/fpcvt]]
+
+Variants only available under the [[sv/svp64]] namespace
+
+* [[isa/svfixedload]]
+* [[isa/svfparith]]
+
+# Pseudocode syntax
+
+The syntax is shown in the v3.0B OpenPOWER Reference Manual. The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
+
+The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first). Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not. Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax. Thus the following pseudocode:
+
+ if x = 1 then
+ RT <- 1
+ else
+ RT <- 0
+
+results in the parser seeing the following python code:
+
+ if x == 1:
+ RT = 1
+ else
+ RT = 0
+
+To support this python-like syntax some of the pseudocode after extraction from the PDF had to be cleaned up and proper indentation added.
+
+Also worth noting as used in the above example: the following operators are used (see section 1.3 "Notation" of v3.0B PDF):
+
+* `<-` assignment, instead of "=" as in python
+* `=` equals comparator, instead of "==" as in python
+* `||` concatenate, done bitwise, in MSB0 order.
+* `>u` for unsigned greater (">" is signed)
+* `<u` for unsigned lessthan ("<" is signed)
+* X superscript n subscript is instead expressed `[X]*n`
+* X subscript n or n:m is expressed as `X[n:m]`
-# Major opcode map
-
-Table 9: Primary Opcode Map (opcode bits 0:5)
-
- 000 001 010 011 100 101 110 111
- 000 tdi
- twi EXT04 mulli 000
- PPC D P1 D {extended} P1 D
- 8 I9 10 I 11 I 12 I 13 I 14 I 15 I
- 001 subfic cmpli cmpi addic addic. addi addis 001
- P1 D {reserved} P1 D P1 D P1 D P1 D P1 D P1 D
- 16 I 17 18 I 19 20 I 21 I 22 23 I
- 010 bc[l][a] EXT17 b[l][a] EXT19 rlwimi[.] rlwinm[.] rlwnm[.] 010
- P1 B {extended} P1 I {extended} P1 M P1 M {reserved} P1 M
- 24 I 25 I 26 I 27 I 28 I 29 I 30 31
- 011 ori oris xori xoris andi. andis. EXT30 EXT31 011
- P1 D P1 D P1 D P1 D P1 D P1 D {extended} {extended}
- 32 I 33 I 34 I 35 I 36 I 37 I 38 I 39 I
- 100 lwz lwzu lbz lbzu stw stwu stb stbu 100
- P1 D P1 D P1 D P1 D P1 D P1 D P1 D P1 D
- 40 I 41 I 42 I 43 I 44 I 45 I 46 I 47 I
- 101 lhz lhzu lha lhau sth sthu lmw stmw 101
- P1 D P1 D P1 D P1 D P1 D P1 D P1 D P1 D
- 48 I 49 I 50 I 51 I 52 I 53 I 54 I 55 I
- 110 lfs lfsu lfd lfdu stfs stfsu stfd stfdu 110
- P1 D P1 D P1 D P1 D P1 D P1 D P1 D P1 D
- 56 I 57 58 59 60 61 62 63
- 111 lq EXT57 EXT58 EXT59 EXT60 EXT61 EXT62 EXT63 111
- v2.03 DQ {extended} {extended} {extended} {extended} {extended} {extended} {extended}
- 000 001 010 011 100 101 110 111
+The reason for the addition of the unsigned comparator operators is because numbers in the pseudocode are bitpatterns, not assigned a type or a sign as would normally be done in a standard programming language
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