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[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 2e1e54466ac9c2e6d37abc7bcb51f5cbc369a4f7..df1797b0b8752dee2ab4beb493952eb1b2854819 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -35,13 +35,17 @@ Scalar instructions added as part of [[sv/svp64]] development, these are
 all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
 on Simple-V).
 Explanation of the rules for twin register targets
-(implicit RS, FRS) explained in SVPY4 [[sv/svp64/appendix]]
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
 
-* [[isa/svfixedload]] DEPRECATED, do not use.
 * [[isa/svfixedarith]]
 * [[isa/svfparith]]
 * [[isa/bitmanip]]
 
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+
 Part of the DRAFT Simple-V Specification:
 
 * [[isa/simplev]]