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[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index e95f720727947964b7a22f22d4810910b5fccb2f..df1797b0b8752dee2ab4beb493952eb1b2854819 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -2,7 +2,9 @@
 
 <!-- this is a test comment -->
 
-ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
+the: CPU instructions, register set, memory model, etc, that describe
+the way a machine works.
 
 These pages contain (in a strict machine-readable subset of mdwn)
 the pseudo-code for all opcodes in the POWER v3.0B Public Spec
@@ -20,7 +22,6 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/sprset]]
 * [[isa/stringldst]]
 * [[isa/system]]
-* [[isa/simplev]]
 
 FP instructions: useful for testing <http://weitz.de/ieee/>
 
@@ -30,6 +31,27 @@ FP instructions: useful for testing <http://weitz.de/ieee/>
 * [[isa/fparith]]
 * [[isa/fpcvt]]
 
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+* [[isa/bitmanip]]
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+
+Part of the DRAFT Simple-V Specification:
+
+* [[isa/simplev]]
+
+A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
+
 # Pseudocode syntax
 
 The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>