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[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 4a039a2b31daa6de6de9bb14f9ca82d9f2bd974c..df1797b0b8752dee2ab4beb493952eb1b2854819 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -1,6 +1,10 @@
 # ISA Pseudo-code 
 
-ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+<!-- this is a test comment -->
+
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
+the: CPU instructions, register set, memory model, etc, that describe
+the way a machine works.
 
 These pages contain (in a strict machine-readable subset of mdwn)
 the pseudo-code for all opcodes in the POWER v3.0B Public Spec
@@ -19,9 +23,38 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/stringldst]]
 * [[isa/system]]
 
+FP instructions: useful for testing <http://weitz.de/ieee/>
+
+* [[isa/fpload]]
+* [[isa/fpstore]]
+* [[isa/fpmove]]
+* [[isa/fparith]]
+* [[isa/fpcvt]]
+
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+* [[isa/bitmanip]]
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+
+Part of the DRAFT Simple-V Specification:
+
+* [[isa/simplev]]
+
+A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
+
 # Pseudocode syntax
 
-The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/pseudo/parser.py;hb=HEAD>
+The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
 
 The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first).  Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not.  Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax.  Thus the following pseudocode:
 
@@ -39,10 +72,15 @@ results in the parser seeing the following python code:
 
 To support this python-like syntax some of the pseudocode after extraction from the PDF had to be cleaned up and proper indentation added.
 
-Also worth noting as used in the above example: the following operators are used:
+Also worth noting as used in the above example: the following operators are used (see section 1.3 "Notation" of v3.0B PDF):
 
 * `<-` assignment, instead of "=" as in python
 * `=` equals comparator, instead of "==" as in python
 * `||` concatenate, done bitwise, in MSB0 order.
-* `>u' for unsigned greater (">" is signed)
-* `<u' for unsigned lessthan ("<" is signed)
+* `>u` for unsigned greater (">" is signed)
+* `<u` for unsigned lessthan ("<" is signed)
+* X superscript n subscript is instead expressed `[X]*n`
+* X subscript n or n:m is expressed as `X[n:m]`
+
+The reason for the addition of the unsigned comparator operators is because numbers in the pseudocode are bitpatterns, not assigned a type or a sign as would normally be done in a standard programming language
+