bug 1168 was marked as a duplicate of bug 1169

[libreriscv.git] / openpower / isa.mdwn

diff --git a/openpower/isa.mdwn b/openpower/isa.mdwn
index 30c73ac0f02906024a841a62aeb3124f41488abd..df1797b0b8752dee2ab4beb493952eb1b2854819 100644 (file)
--- a/openpower/isa.mdwn
+++ b/openpower/isa.mdwn
@@ -2,7 +2,9 @@
 
 <!-- this is a test comment -->
 
-ISA is the [[!wikipedia Instruction_set_architecture]] of a machine, the: CPU instructions, register set, memory model, etc, that describe the way a machine works.
+ISA is the [[!wikipedia Instruction_set_architecture]] of a machine,
+the: CPU instructions, register set, memory model, etc, that describe
+the way a machine works.
 
 These pages contain (in a strict machine-readable subset of mdwn)
 the pseudo-code for all opcodes in the POWER v3.0B Public Spec
@@ -20,7 +22,6 @@ the pseudo-code for all opcodes in the POWER v3.0B Public Spec
 * [[isa/sprset]]
 * [[isa/stringldst]]
 * [[isa/system]]
-* [[isa/simplev]]
 
 FP instructions: useful for testing <http://weitz.de/ieee/>
 
@@ -28,10 +29,32 @@ FP instructions: useful for testing <http://weitz.de/ieee/>
 * [[isa/fpstore]]
 * [[isa/fpmove]]
 * [[isa/fparith]]
+* [[isa/fpcvt]]
+
+Scalar instructions added as part of [[sv/svp64]] development, these are
+all **DRAFT FORM** and they are all stand-alone Scalar (no hard dependency
+on Simple-V).
+Explanation of the rules for twin register targets
+(implicit RS, FRS) explained in SVP64 [[sv/svp64/appendix]]
+
+* [[isa/svfixedarith]]
+* [[isa/svfparith]]
+* [[isa/bitmanip]]
+
+Scalar "Post-Increment" Draft Load/Store with Update
+
+* [[isa/pifixedload]]
+* [[isa/pifixedstore]]
+
+Part of the DRAFT Simple-V Specification:
+
+* [[isa/simplev]]
+
+A useful aide to finding Power ISA instructions: <https://power-isa-beta.mybluemix.net>
 
 # Pseudocode syntax
 
-The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/decoder/pseudo/parser.py;hb=HEAD>
+The syntax is shown in the v3.0B OpenPOWER Reference Manual.  The implementation of a parser, using python-ply, is here: <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/pseudo/parser.py;hb=HEAD>
 
 The parser is based on the python-ply GardenSnake.py example (except bugs were fixed in it, first).  Extra tokens, in the lexer phase, are inserted dynamically into the stream to make the parser think that it is seeing python-like syntax where in fact it is not.  Example: when a pseudocode keyword "THEN" is seen, this is substituted for ":". The keyword "ELSE" will also automatically have a second ":" token inserted in order to comply with python syntax.  Thus the following pseudocode: