replace XOR with ^ operator

[libreriscv.git] / openpower / isatables.mdwn

diff --git a/openpower/isatables.mdwn b/openpower/isatables.mdwn
index 226e612f6727ded48707ea3e2e87fd166d017224..6ae8503498c9e025d2c154c9094e57c0eddef38f 100644 (file)
--- a/openpower/isatables.mdwn
+++ b/openpower/isatables.mdwn
@@ -1,34 +1,62 @@
 # ISA Reference Tables
 
-TODO
-
-Based on Anton Blanchard's microwatt decode1.vhdl
+These are from 3.0B p1145 Appendix C, and are
+based on Anton Blanchard's microwatt decode1.vhdl
 
 # Major opcodes
 
+decodes using f_in.insn(31 downto 26)
+
 [[!table format=csv file="openpower/isatables/major.csv"]]
 
 # Minor opcode 19
 
+decodes using f_in.insn(5 downto 1)
+
+[[!table format=csv file="openpower/isatables/minor_19_00000.csv"]]
+
+decodes using f_in.insn(10 downto 1)
+
 [[!table format=csv file="openpower/isatables/minor_19.csv"]]
 
 # Minor opcode 30
 
+decodes using f_in.insn(4 downto 1)
+
 [[!table format=csv file="openpower/isatables/minor_30.csv"]]
 
 # Minor opcode 31
 
+decodes using f_in.insn(10 downto 1)
+
 [[!table format=csv file="openpower/isatables/minor_31.csv"]]
 
 # Minor opcode 58
 
+decodes using f_in.insn(1 downto 0)
+
 [[!table format=csv file="openpower/isatables/minor_58.csv"]]
 
 # Minor opcode 62
 
+decodes using f_in.insn(1 downto 0)
+
 [[!table format=csv file="openpower/isatables/minor_62.csv"]]
 
 # Extra opcodes
 
+These can match against the (full) row[0] spec: nmigen Case supports "-" as
+"don't care"
+
 [[!table format=csv file="openpower/isatables/extra.csv"]]
 
+# SPRs
+
+Special Purpose Registers.  These are listed in 3.0B Table 18 p971.
+
+[[!table format=csv file="openpower/isatables/sprs.csv"]]
+
+# Fields
+
+These can be downloaded in plain text format here:
+<http://libre-riscv.org/openpower/isatables/fields.text>