updating sv_analys.py svp64 table

[libreriscv.git] / openpower / opcode_regs_deduped.mdwn

diff --git a/openpower/opcode_regs_deduped.mdwn b/openpower/opcode_regs_deduped.mdwn
index 16716967171e5115cdecd3ff878c7cb40c9a35de..cfc3dd65d2f08ee948dfddabfa8fd0448e941dce 100644 (file)
--- a/openpower/opcode_regs_deduped.mdwn
+++ b/openpower/opcode_regs_deduped.mdwn
@@ -975,9 +975,9 @@ divwo | 1P | EXTRA3 | d:RT,d:CR0 | s:RA | s:RB |  | RA | RB | NONE | RT | NONE |
 
 [[!table  data="""
 insn | Ptype | Etype | 0 | 1 | 2 | 3 |
-rlwimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
-rldimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
-rldimi | 1P | EXTRA3 | TODO |  |  |  | RA |  | RS | RA | NONE | CR0 |
+rlwimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
+rldimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
+rldimi | 1P | EXTRA3 | d:RA,d:CR0 | s:RA | s:RS |  | RA |  | RS | RA | NONE | CR0 |
 """]]
 
 ## 2R-1W-CRi (RM-1P-3S1D)