\usepackage{sectsty}
\usepackage{appendix}
\usepackage{graphicx}
+\usepackage[firstpage]{draftwatermark}
+\usepackage[printonlyused,withpage]{acronym}
+\usepackage{float}
+\usepackage{url}
+\usepackage[useregional]{datetime2}
\usepackage{anyfontsize}
\usepackage{ifxetex,ifluatex}
\usepackage{fixltx2e} % provides \textsubscript
}{}
\PassOptionsToPackage{hyphens}{url} % url is loaded by hyperref
\usepackage[unicode=true]{hyperref}
-\hypersetup{
- pdfborder={0 0 0},
+\hypersetup{colorlinks=true,
+ linkcolor=blue,
+ filecolor=cyan,
+ urlcolor=magenta,
breaklinks=true}
\usepackage[margin=0.9in]{geometry}
\usepackage{color}
\newcommand{\ErrorTok}[1]{\textcolor[rgb]{1.00,0.00,0.00}{\textbf{#1}}}
\newcommand{\NormalTok}[1]{#1}
+% these come from:
+% https://gist.github.com/bgeron/72ebbacf5930537022079d9953f15713
+\usepackage{newunicodechar}
+\newcommand\DeclareUnicodeInv[2]{\DeclareUnicodeCharacter{#2}{#1}}
+
+\DeclareUnicodeCharacter{03A0}{\ensuremath{\Pi}}
+\DeclareUnicodeCharacter{2208}{\ensuremath{\in}}
+\DeclareUnicodeCharacter{03C0}{\ensuremath{\pi}}
+\DeclareUnicodeCharacter{221A}{$\sqrt{}$}
+\DeclareUnicodeCharacter{221B}{$\sqrt[3]{}$}
+\DeclareUnicodeInv{\ensuremath{\mathbb{Z}}}{2124}
+
% indent all verbatim
\catcode`\@=11
\let \saveverbatime \@xverbatim
\def\fps@figure{htbp}
\makeatother
+% graphics path for primer
+\graphicspath{ {svp64-primer/img/} }
\date{}
\chapter*{Preamble}
\addcontentsline{toc}{chapter}{Preamble} \markboth{INTRODUCTION}{}
+\textbf{Last modified date: \today}
+
This document is an auto-generated version of the Draft SVP64
Specification available at
Process. Funding from NLnet, through their Privacy and Enhanced Trust
Programme, requires full transparency.
+As this document is under continuous rapid revision please check frequently
+at:
+
+\begin{verbatim}
+ https://ftp.libre-soc.org/simple_v_spec.pdf
+\end{verbatim}
+
+\subsection*{Contacts}
+For questions, comments, and clarification, please contact the following:
+\begin{itemize}
+ \itemsep -0.3em
+ \item Libre-SOC ISA Dev Mailing List - libre-soc-isa@lists.libre-soc.org
+ \item Luke Kenneth Casson Leighton - Libre-SOC team lead and Red
+ Semiconductor Ltd Director - lkcl@lkcl.net
+ \item David Calderwood - Red Semiconductor Ltd Director -
+ djac@calderwoodhan.com
+ \item Toshaan Bharvani - OpenPOWER Foundation Technical Chair, VanTosh
+ Director - toshaan@vantosh.com
+ \item Konstantinos Margaritis - Engineer and Founder of VectorCamp, writing optimised assembler for a number of SIMD/Vector ISAs - konstantinos@vectorcamp.gr
+ \item Dmitry Selyutin - Libre-SOC engineer, working on binutils SVP64 assembler - ghostmansd@gmail.com
+ \item Jacob Lifshay - Libre-SOC engineer, CPU arch and verification - programmerjake@gmail.com
+ \item Cesar Strauss - Libre-SOC engineer, CPU arch and verification - cestrauss@gmail.com
+ \item Andrey Miroshnikov - Libre-SOC engineer, assisting with documentation - andrey@technepisteme.xyz
+\end{itemize}
+
+\newpage
+\subsection*{Executive Summary}
+\hypertarget{svux2fexecutive_summary}{}
+\input{tex_out/executive_summary.tex}
+
+\newpage
+\begin{landscape}
+\addcontentsline{toc}{chapter}{Comparison Table} \markboth{INTRODUCTION}{}
+\hypertarget{svux2fcomparison_table}{}
+{
+\fontsize{6}{8}\selectfont
+\input{tex_out/comparison_table.tex}
+}
+\end{landscape}
+
+\part{Scalable Vectors Primer}
+\input{svp64-primer/acronyms}
+%\chapter*{Executive Summary}
+\include{svp64-primer/summary}
+\bibliography{svp64-primer/references}
+\bibliographystyle{ieeetr}
+
\tableofcontents
-\part{Scalable Vectors}
+% Part II
+\part{Scalable Vectors for the Power ISA}
+
\chapter{Fields and Forms}
\hypertarget{svux2ffields}{}
\input{tex_out/sv.tex}
\chapter{Other Vector ISAs}\hypertarget{svux2fvector_isa_comparison}{}
\input{tex_out/vector_isas.tex}
-\chapter{Comparison Table}\hypertarget{svux2fcomparison_table}{}
-\input{tex_out/comparison_table.tex}
\chapter{Overview}\hypertarget{svux2foverview}{}
\input{tex_out/overview.tex}
\chapter{Compliancy Levels}\hypertarget{svux2fcompliancy_levels}{}
\input{tex_out/remap_appendix.tex}
\chapter{Simple-V pseudocode}\hypertarget{svux2fpseudocode_simplev}{}
\input{tex_out/pseudocode_simplev.tex}
+\chapter{Simple-V Analysis}\hypertarget{svux2fsv_analysis}{}
+\input{tex_out/sv_analysis.tex}
+
\chapter{SVP64 Augmentation Table}\hypertarget{opcode_regs_deduped}{}
\begin{landscape}
{
\input{tex_out/opcode_regs_deduped.tex}
}
\end{landscape}
+
\end{appendices}
+% Part III
\part{Scalar Instructions}
-\chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
+\chapter*{Preamble}{}
+
+As explained in the Simple-V introduction
+these are all intentionally and specifically Scalar instructions.
+Each section is free-standing, has no connection, dependence or
+relationship to any other section, including no direct critical dependence
+either way on Simple-V.
+They have with almost no exceptions been specifically crafted to
+have a justification for their inclusion in the Power ISA as Scalar
+instructions purely on their own merit.
+
+\begin{itemize}
+ \item The biginteger multiply-and-add instruction is similar
+ to Intel's mulx in that it produces a pair of results.
+ \item JavaScript(tm) rounding is present in ARM as fjcvtzs
+ and would save an astounding 35 instructions with 5 branches.
+ \item Whilst there exist CR bit manipulation and copying
+ instructions there are no CR Field manipulation instructions,
+ putting pressure on GPRs if several CR fits need to be analysed.
+ \item one single instruction, bmask, is proposed that covers
+ the whole of x86 BMI1 and AMD TBM, combined, and provides more.
+\end{itemize}
+
+All of these have nothing to do with Simple-V at all: they make
+the Power ISA better at modern general-purpose compute, bringing
+it up-to-date.
+
+That said: by a wonderful coincidence, should they be included, then
+Simple-V's capabilities increase significantly. For example the CRweird
+instructions combined with the bitmanip instructions, alongside
+Vectorised Rc=1 turn CR Fields into
+extremely powerful Predicate masks. bmask not only
+covers the BMI and TBM instructions of Intel and AMD it also
+includes the RVV set-before-first and set-after-first instructions.
+
+The clean and clear separation between Vectorisation Prefix and Scalar
+Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
+to benefit. It also makes proposal much easier, as there is no
+inter-dependence.
+
+It is however important to note that the rationale for these instructions
+comes from a more general-purpose modern computing paradigm that is
+outside of IBM's much more focussed and specialist traditional customer
+base. We deeply respect IBM's curator role of the Power ISA of the past 25
+years as much as we appreciate their courage in transferring that role
+to the OpenPOWER Foundation ISA Working Group.
+
+\chapter{SV Vector-assist Scalar ops}\hypertarget{svux2fvector_ops}{}
\input{tex_out/vector_ops.tex}
\chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
\hypertarget{cr_int_predication}{}
\input{tex_out/big_integer.tex}
\chapter{Transcendentals}\hypertarget{transcendentals}{}
\input{tex_out/transcendentals.tex}
-\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
-\input{tex_out/atomics.tex}
+%\chapter{Acquire/Release Atomic Memory}\hypertarget{atomics}{}
+%\input{tex_out/atomics.tex}
\begin{appendices}
\chapter{Big Integer Analysis}\hypertarget{svux2fbigintegerux2fanalysis}{}
\input{tex_out/pseudocode_svfixedarith.tex}
\end{appendices}
+% Part IV
\part{Scalar Power ISA pseudocode}
\backmatter % temporary fix for too many appenfices
%\setcounter{chapter}{0}
projects / libreriscv.git / blobdiff