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[libreriscv.git] / openpower / sv / 16_bit_compressed.mdwn

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 9e77446550bf15730bcfb67b66f4a6e9ab447655..2a302ea5d7d9929ad1e50f3cc37bf47622964086 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # 16 bit Compressed
 
 Similar to VLE (but without immediate-prefixing) this encoding is designed
@@ -111,7 +113,9 @@ to cross into or out of a function call.
 Thus it is the mandatory responsibility of the compiler to ensure that
 context returns to "v3.0B Standard" prior to entering a function call
 (responsibility of caller) and prior to exit from a function call
-(responsibility of callee).
+(responsibility of callee) by setting appropriate M and N bits.
+
+If however it is known to the compiler that certain static leaf node functions and their immediate callers will never, under any circumstances, be called by externsl ABI compliant code, then of course the compiler may choose to write such static functions as it sees fit.
 
 Trap Handlers also take responsibility for saving and restoring of
 Compressed Mode state, just as they already take responsibility for
@@ -238,7 +242,8 @@ instruction counts from objdump on /bin/bash:
     | 1 | 1  | 0 | sh2 | | 001.0 | RA   | sh  | 1 | srawi.
     | 1 | 1  | 1 |     | | 001.0 | 000  | imm | 1 | TBD
     | 1 | 1  | 1 | i2  | | 001.0 | RA!=0| imm | 1 | addis
-    | 1 |              | | 010.0 | 000  |     | 1 | TBD
+    | 1 | 0  | i2      | | 010.0 | 000  | imm | 1 | setvli
+    | 1 | 1  | i2      | | 010.0 | 000  | imm | 1 | setmvli
     | 1 | i2           | | 010.0 | RA!=0| imm | 1 | addi
     | 1 | 0  | i2      | | 010.1 | RA   | imm | 1 | cmpdi
     | 1 | 1  | i2      | | 010.1 | RA   | imm | 1 | cmpwi
@@ -322,7 +327,7 @@ In essence the 2 nops are needed due to there being 2 different C forms:
 
 ### Branch
 
-TODO: document that branching whilst using mode-switching bits (M/N) is perfectly well permitted but is specifically and wholly the complier/assembler writers responsibility to obey ABI rules and ensure that even with branches and returns that, at no time, is an incorrect mode entered or left that could result in any instruction being misinterpreted.
+TODO: document that branching whilst using mode-switching bits (M/N) is perfectly well permitted, the caveat being: it is specifically and wholly the complier/assembler writers responsibility to obey ABI rules and ensure that even with branches and returns that, at no time, is an incorrect mode entered or left that could result in any instruction being misinterpreted.
 
     | 16-bit mode | | 10-bit mode                 |
     | 0 | 1 | 234 | | 567.8  | 9  ab | c   de | f |
@@ -429,9 +434,9 @@ Notes:
     | N | 0 |  RT | | 100.1 | RB  | RA!=0 | M | nand
     | N | 0 |  RT | | 101.0 | RB  | RA!=0 | M | or
     | N | 0 |  RT | | 101.1 | RB  | RA!=0 | M | nor/mr
-    | N | 0 |  RT | | 100.0 | RB  | 0 0 0 | M | extsw
+    | N | 0 |  RT | | 100.0 | RB  | 0 0 0 | M | popcnt
     | N | 0 |  RT | | 100.1 | RB  | 0 0 0 | M | cntlz
-    | N | 0 |  RT | | 101.0 | RB  | 0 0 0 | M | popcnt
+    | N | 0 |  RT | | 101.0 | RB  | 0 0 0 | M | extsw
     | N | 0 |  RT | | 101.1 | RB  | 0 0 0 | M | not
 
 16-bit mode only (note that bit 1 == 1):
@@ -442,9 +447,9 @@ Notes:
     | N | 1 |  RT | | 100.1 | RB  | RA!=0 | M | TBD
     | N | 1 |  RT | | 101.0 | RB  | RA!=0 | M | xor
     | N | 1 |  RT | | 101.1 | RB  | RA!=0 | M | eqv (xnor)
-    | N | 1 |  RT | | 100.0 | RB  | 0 0 0 | M | extsb
+    | N | 1 |  RT | | 100.0 | RB  | 0 0 0 | M | setvl.
     | N | 1 |  RT | | 100.1 | RB  | 0 0 0 | M | cnttz
-    | N | 1 |  RT | | 101.0 | RB  | 0 0 0 | M | TBD
+    | N | 1 |  RT | | 101.0 | RB  | 0 0 0 | M | extsb
     | N | 1 |  RT | | 101.1 | RB  | 0 0 0 | M | extsh
 
 10 bit mode:
@@ -578,9 +583,9 @@ space (when RA==0)
     | N | 1 | 111 | | 001.1 | 0 10 |      | M |
     | N | 1 | 111 | | 001.1 | 0 11 |      | M |
 
-## Other ideas (Attempt 2)
+# Other ideas (Attempt 2)
 
-### 8-bit mode-switching instructions, odd addresses for C mode
+## 8-bit mode-switching instructions, odd addresses for C mode
 
 Drop the complexity of the 16-bit encoding further reduced to 10-bit,
 and use a single byte instead of two to switch between modes.  This
@@ -623,6 +628,14 @@ Tables explaining encoding:
     | .. bit | 16 bit          | 8nop   |
     | v3.0B standard 32 bit instruction |
 
+# Other ideas (v3)
+
+FSM state switching and mode switching deemed too complex.  Instead cut back to
+
+1. 10bit only (actually, 11 bit)
+2. SV-Prefixed 16bit only (aka SV-C32)
+
+Each will be entirely different which is a huge amount of work.
 
 # TODO