(no commit message)

[libreriscv.git] / openpower / sv / 16_bit_compressed.mdwn

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 4d24c01cb8d631b185f5585fc1aee70f5d4432e3..564138e1b85b113924a28940363cf4287ace45e9 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # 16 bit Compressed
 
 Similar to VLE (but without immediate-prefixing) this encoding is designed
@@ -39,7 +41,7 @@ standard 32 bit and 16 bit to intermingle cleanly.  To achieve the same
 thing on OpenPOWER would require a whopping 24 6-bit Major Opcodes which
 is clearly impractical: other schemes need to be devised.
 
-In addition we would like to add SV-C32 which is a Vectorised version
+In addition we would like to add SV-C32 which is a Vectorized version
 of 16 bit Compressed, and ideally have a variant that adds the 27-bit
 prefix format from SV-P64, as well.
 
@@ -581,9 +583,9 @@ space (when RA==0)
     | N | 1 | 111 | | 001.1 | 0 10 |      | M |
     | N | 1 | 111 | | 001.1 | 0 11 |      | M |
 
-## Other ideas (Attempt 2)
+# Other ideas (Attempt 2)
 
-### 8-bit mode-switching instructions, odd addresses for C mode
+## 8-bit mode-switching instructions, odd addresses for C mode
 
 Drop the complexity of the 16-bit encoding further reduced to 10-bit,
 and use a single byte instead of two to switch between modes.  This
@@ -626,6 +628,14 @@ Tables explaining encoding:
     | .. bit | 16 bit          | 8nop   |
     | v3.0B standard 32 bit instruction |
 
+# Other ideas (v3)
+
+FSM state switching and mode switching deemed too complex.  Instead cut back to
+
+1. 10bit only (actually, 11 bit)
+2. SV-Prefixed 16bit only (aka SV-C32)
+
+Each will be entirely different which is a huge amount of work.
 
 # TODO