+[[!tag standards]]
+
# 16 bit Compressed
Similar to VLE (but without immediate-prefixing) this encoding is designed
thing on OpenPOWER would require a whopping 24 6-bit Major Opcodes which
is clearly impractical: other schemes need to be devised.
-In addition we would like to add SV-C32 which is a Vectorised version
+In addition we would like to add SV-C32 which is a Vectorized version
of 16 bit Compressed, and ideally have a variant that adds the 27-bit
prefix format from SV-P64, as well.
If NNNNN is the same value (two contiguous Major v3.0B Opcodes) this
saves gates at a critical part of the decode phase.
-## Comparison to VLE
-
-VLE was a means to reduce executable size through three interleaved methods:
-
-* (1) invention of 16 bit encodings (of exactly 16 bit in length)
-* (2) invention of 16+16 bit encodings (a 16 bit instruction format but with
- an *additional* 16 bit immediate "tacked on" to the end, actually
- making a 32-bit instruction format)
-* (3) seamless and transparent embedding and intermingling of the
- above in amongst arbitrary v2.06/7 BE 32 bit instruction sequences,
- with no additional state,
- including when the PC was not aligned on a 4-byte boundary.
-
-Whilst (1) and (3) make perfect sense, (2) makes no sense at all given that, as inspection of "ori" and others show, I-Form 16 bit immediates is the "norm" for v2.06/7 and v3.0B standard instructions. (2) in effect **is** a 32 bit instruction. (2) **is not** a 16 bit instruction.
-
-*Why "reinvent" an encoding that is 32 bit, when there already exists a 32 bit encoding that does the exact same job?*
-
-Consequently, we do **not** envisage a scenario where (2) would ever be implemented, nor in the future would this Compressed Encoding be extended beyond 16 bit. Compressed is Compressed and is **by definition** limited to precisely - and only - 16 bit.
-
-The additional reason why that is the case is because VLE is exceptionally complex to implement. In a single-issue, low clock rate "Embedded" environment for which VLE was originally designed, VLE was perfectly well matched.
-
-However this Compressed Encoding is designed for High performance multi-issue systems *as well* as Embedded scenarios, and consequently, the complexity of "deep packet inspection" down into the depths of a 16 bit sequence in order to ascertain if it might not be 16 bit after all, is wholly unacceptable.
-
-By eliminating such 16+16 (actually, 32bit conflation) tricks outlined in (2), Compressed is *specifically* designed to fit into a very small FSM, suitable for multi-issue, that in no way requires "deep-dive" analysis. Yet, despite it never being designed with 16 bit encodings in mind, is still suitable for retro-fitting onto OpenPOWER.
-
## ABI considerations
Unlike RISC-V RVC, the above "context" encodings require state, to be stored
Thus it is the mandatory responsibility of the compiler to ensure that
context returns to "v3.0B Standard" prior to entering a function call
(responsibility of caller) and prior to exit from a function call
-(responsibility of callee).
+(responsibility of callee) by setting appropriate M and N bits.
+
+If however it is known to the compiler that certain static leaf node functions and their immediate callers will never, under any circumstances, be called by externsl ABI compliant code, then of course the compiler may choose to write such static functions as it sees fit.
Trap Handlers also take responsibility for saving and restoring of
Compressed Mode state, just as they already take responsibility for
16-bit immediate mode remains in 16-bit.
| 0 | 1234 | 567 8 | 9abcde | f | explanation
+ | - | ---- | ------ | ------ | - | -----------
| EXT000/1 | Cmaj.m | fields | 0 | 10bit then v3.0B
| EXT000/1 | Cmaj.m | fields | 1 | 10bit then 16bit
| 0 | flds | Cmaj.m | fields | 0 | 16bit then v3.0B
| 0 | flds | Cmaj.m | fields | 1 | 16bit then 16bit
- | 1 | flds | Cmaj.m | fields | 0 | 16b then 1x v3.0B
+ | 1 | flds | Cmaj.m | fields | 0 | 16b, 1x v3.0B, 16b
| 1 | flds | Cmaj.m | fields | 1 | 16b/imm then 16bit
Notes:
are zero, therefore the 6th bit is actually part of Cmaj.
* "10bit then 16bit" means "this instruction is encoded C 10bit
and the following one in C 16bit"
+* "16b, 1x v3.0B, 16b" means, "this instruction is encoded C 16bit,
+ the following one is V3.0B Standard, and the one after that is
+ back to 16bit".
### C Instruction Encoding types
| 0 | 1234 | 567 8 | 9 | a b | c | d e | f | enc
| N | immf | Cmaj.m | fld1 | fld2 | M | 16b
| 1 | immf | Cmaj.m | fld1 | imm | 1 | 16b imm
- | fd3 | 001.1 | S1 | fd1 | S2 | fd2 | M | 16b sub
+ | N | fd3 | 001.1 | S1 | fd1 | S2 | fd2 | M | 16b sub
| N | fd4 | 111.m | fld1 | fld2 | M | 16b LDST
Notes:
| 1 | 1 | 0 | sh2 | | 001.0 | RA | sh | 1 | srawi.
| 1 | 1 | 1 | | | 001.0 | 000 | imm | 1 | TBD
| 1 | 1 | 1 | i2 | | 001.0 | RA!=0| imm | 1 | addis
- | 1 | | | 010.0 | 000 | | 1 | TBD
+ | 1 | 0 | i2 | | 010.0 | 000 | imm | 1 | setvli
+ | 1 | 1 | i2 | | 010.0 | 000 | imm | 1 | setmvli
| 1 | i2 | | 010.0 | RA!=0| imm | 1 | addi
| 1 | 0 | i2 | | 010.1 | RA | imm | 1 | cmpdi
| 1 | 1 | i2 | | 010.1 | RA | imm | 1 | cmpwi
16 bit mode only:
+ | 0 | 1 | 234 | | 567.8 | 9 ab | c de | f |
| - | - | --- | | ----- | ----- | ------ | - |
| 1 | 0 000 | | 000.0 | 0 00 | 0 00 | 0 | nop
- | 1 | 1 000 | | 000.0 | 0 00 | 0 00 | 0 | attn
- | 1 | nonzero | | 000.0 | 0 00 | 0 00 | 0 | TBD
+ | 1 | 0 000 | | 000.0 | 0 00 | 0 00 | 1 | nop
+ | N | 1 000 | | 000.0 | 0 00 | 0 00 | M | attn
Notes:
### Branch
+TODO: document that branching whilst using mode-switching bits (M/N) is perfectly well permitted, the caveat being: it is specifically and wholly the complier/assembler writers responsibility to obey ABI rules and ensure that even with branches and returns that, at no time, is an incorrect mode entered or left that could result in any instruction being misinterpreted.
+
| 16-bit mode | | 10-bit mode |
| 0 | 1 | 234 | | 567.8 | 9 ab | c de | f |
| - | - | --- | | ----- | ----- | ------ | - |
| N | offs2 | | 000.LK | offs!=0 | M | b, bl
+ | N | | | 000.1 | 0 00 | 0 00 | M | TBD
| 1 | offs2 | | 000.LK | BI | BO1 oo | 1 | bc, bcl
| N | BO3 BI3 | | 001.0 | LK BI | BO | M | bclr, bclrl
Note: for 10-bit, ignore bits 0-4 (used by EXTNNN=Compressed)
- | 16-bit mode | | 10-bit mode |
- | 0 | 1 | 234 | | 567.8 | 9 a b | c d e | f |
- | --- | -- | --- | | ----- | ----- | ----- | - |
- | RA2 | SZ | RB | | 001.1 | 1 RA | 0 RT | M | st
- | RA2 | SZ | RB | | 001.1 | 1 RA | 1 RT | M | fst
- | N | SZ | RT | | 111.0 | RA | RB | M | ld
- | N | SZ | RT | | 111.1 | RA | RB | M | fld
+ | 16-bit mode | | 10-bit mode |
+ | 0 | 1 | 234 | | 567.8 | 9 a b | c d e | f |
+ | - | -- | --- | | ----- | ----- | ----- | - |
+ | N | SZ | RB | | 001.1 | 1 RA | 0 RT | M | st
+ | N | SZ | RB | | 001.1 | 1 RA | 1 RT | M | fst
+ | N | SZ | RT | | 111.0 | RA | RB | M | ld
+ | N | SZ | RT | | 111.1 | RA | RB | M | fld
* elwidth overrides can set different widths
16 bit mode:
* SZ=1 is 64 bit, SZ=0 is 32 bit
-* RA2 extends RA to 3 bits (MSB)
-* RT2 extends RT to 3 bits (MSB)
10 bit mode:
* 10-bit, ignore bits 0-4 (used by EXTNNN=Compressed)
* 16-bit: note that bit 1==0 (sub-sub-encoding)
+10 and 16 bit:
+
| 16-bit mode | | 10-bit mode |
| 0 | 1 | 234 | | 567.8 | 9ab | c d e | f |
| - | - | --- | | ----- | --- | ----- | - |
| 0 | 1 | 234 | | 567.8 | 9ab | cde | f |
| - | - | --- | | ----- | --- | ----- | - |
- | N | 1 | RA | | 010.0 | RB | RS | 0 | sld.
- | N | 1 | RA | | 010.1 | RB | RS!=0 | 0 | srd.
- | N | 1 | RA | | 010.1 | RB | 000 | 0 | srad.
- | N | 1 | BF | | 011.0 | RB | RA|0 | 0 | cmpw
+ | N | 1 | RA | | 010.0 | RB | RS | M | sld.
+ | N | 1 | RA | | 010.1 | RB | RS!=0 | M | srd.
+ | N | 1 | RA | | 010.1 | RB | 000 | M | srad.
+ | N | 1 | BF | | 011.0 | RB | RA|0 | M | cmpw
Notes:
* 10-bit, ignore bits 0-4 (used by EXTNNN=Compressed)
* 16-bit: note that bit 1==0 (sub-sub-encoding)
+10 and 16 bit:
+
| 16-bit mode | | 10-bit mode |
| 0 | 1 | 234 | | 567.8 | 9ab | c d e | f |
| - | - | --- | | ----- | --- | ----- | - |
| N | 0 | RT | | 100.1 | RB | RA!=0 | M | nand
| N | 0 | RT | | 101.0 | RB | RA!=0 | M | or
| N | 0 | RT | | 101.1 | RB | RA!=0 | M | nor/mr
- | N | 0 | RT | | 100.0 | RB | 0 0 0 | M | extsw
+ | N | 0 | RT | | 100.0 | RB | 0 0 0 | M | popcnt
| N | 0 | RT | | 100.1 | RB | 0 0 0 | M | cntlz
- | N | 0 | RT | | 101.0 | RB | 0 0 0 | M | popcnt
+ | N | 0 | RT | | 101.0 | RB | 0 0 0 | M | extsw
| N | 0 | RT | | 101.1 | RB | 0 0 0 | M | not
16-bit mode only (note that bit 1 == 1):
| 0 | 1 | 234 | | 567.8 | 9ab | c d e | f |
| - | - | --- | | ----- | --- | ----- | - |
- | N | 1 | RT | | 100.0 | RB | RA!=0 | 0 | TBD
- | N | 1 | RT | | 100.1 | RB | RA!=0 | 0 | TBD
- | N | 1 | RT | | 101.0 | RB | RA!=0 | 0 | xor
- | N | 1 | RT | | 101.1 | RB | RA!=0 | 0 | eqv (xnor)
- | N | 1 | RT | | 100.0 | RB | 0 0 0 | 0 | extsb
- | N | 1 | RT | | 100.1 | RB | 0 0 0 | 0 | cnttz
- | N | 1 | RT | | 101.0 | RB | 0 0 0 | 0 | TBD
- | N | 1 | RT | | 101.1 | RB | 0 0 0 | 0 | extsh
+ | N | 1 | RT | | 100.0 | RB | RA!=0 | M | TBD
+ | N | 1 | RT | | 100.1 | RB | RA!=0 | M | TBD
+ | N | 1 | RT | | 101.0 | RB | RA!=0 | M | xor
+ | N | 1 | RT | | 101.1 | RB | RA!=0 | M | eqv (xnor)
+ | N | 1 | RT | | 100.0 | RB | 0 0 0 | M | setvl.
+ | N | 1 | RT | | 100.1 | RB | 0 0 0 | M | cnttz
+ | N | 1 | RT | | 101.0 | RB | 0 0 0 | M | extsb
+ | N | 1 | RT | | 101.1 | RB | 0 0 0 | M | extsh
10 bit mode:
* 10-bit, ignore bits 0-4 (used by EXTNNN=Compressed)
* 16-bit: note that bit 1==0 (sub-sub-encoding)
+10 and 16 bit:
+
| 16-bit mode | | 10-bit mode |
| 0 | 1 | 234 | | 567.8 | 9ab | c d e | f |
| - | - | --- | | ----- | --- | ----- | - |
| N | 0 | RT | | 110.0 | RB | RA!=0 | M | fadd
| N | 0 | RT | | 110.1 | RB | RA!=0 | M | fmul
| N | 0 | RT | | 011.1 | RB | 0 0 0 | M | fneg.
- | N | 0 | RT | | 110.0 | RB | 0 0 0 | M |
- | N | 0 | RT | | 110.1 | RB | 0 0 0 | M |
+ | N | 0 | | | 110.0 | | 0 0 0 | M | TBD
+ | N | 0 | | | 110.1 | | 0 0 0 | M | TND
16-bit mode only (note that bit 1 == 1):
| 0 | 1 | 234 | | 567.8 | 9ab | c d e | f |
| - | - | --- | | ----- | --- | ----- | - |
- | N | 1 | RT | | 011.1 | RB | RA!=0 | 0 |
- | N | 1 | RT | | 110.0 | RB | RA!=0 | 0 |
- | N | 1 | RT | | 110.1 | RB | RA!=0 | 0 | fdiv
- | N | 1 | RT | | 011.1 | RB | 0 0 0 | 0 | fabs.
- | N | 1 | RT | | 110.0 | RB | 0 0 0 | 0 | fmr.
- | N | 1 | RT | | 110.1 | RB | 0 0 0 | 0 |
+ | N | 1 | | | 011.1 | | RA!=0 | M | TBD
+ | N | 1 | | | 110.0 | | RA!=0 | M | TBD
+ | N | 1 | RT | | 110.1 | RB | RA!=0 | M | fdiv
+ | N | 1 | RT | | 011.1 | RB | 0 0 0 | M | fabs.
+ | N | 1 | RT | | 110.0 | RB | 0 0 0 | M | fmr.
+ | N | 1 | | | 110.1 | | 0 0 0 | M | TBD
16 bit only, FP to INT convert (using C 0b001.1 subencoding)
- | 0123 | 4 | | 567.8 | 9 ab | cde | f |
- | ---- | - | | ----- | ---- | ---- | - |
- | 0010 | X | | 001.1 | 0 RA | Y RT | M | fp2int
- | 0011 | X | | 001.1 | 0 RA | Y RT | M | int2fp
+ | 0 | 123 | 4 | | 567.8 | 9 ab | cde | f |
+ | - | --- | - | | ----- | ---- | ---- | - |
+ | N | 101 | X | | 001.1 | 0 RA | Y RT | M | fp2int
+ | N | 110 | X | | 001.1 | 0 RA | Y RT | M | int2fp
* X: signed=1, unsigned=0
* Y: FP32=0, FP64=1
### Condition Register
- | 16-bit mode | | 10-bit mode |
- | 0 1 2 3 | 4 | | 567.8 | 9 ab | cde | f |
- | ------- | --- | | ----- | ---- | --- | - |
- | 0 0 0 0 | BF2 | | 001.1 | 0 BF | BFA | M | mcrf
- | 0 0 0 1 | BA2 | | 001.1 | 0 BA | BB | M | crnor
- | 0 1 0 0 | BA2 | | 001.1 | 0 BA | BB | M | crandc
- | 0 1 1 0 | BA2 | | 001.1 | 0 BA | BB | M | crxor
- | 0 1 1 1 | BA2 | | 001.1 | 0 BA | BB | M | crnand
- | 1 0 0 0 | BA2 | | 001.1 | 0 BA | BB | M | crand
- | 1 0 0 1 | BA2 | | 001.1 | 0 BA | BB | M | creqv
- | 1 1 0 1 | BA2 | | 001.1 | 0 BA | BB | M | crorc
- | 1 1 1 0 | BA2 | | 001.1 | 0 BA | BB | M | cror
+10-bit or 16 bit:
+
+ | 16-bit mode| | 10-bit mode |
+ | 0 | 123 | 4 | | 567.8 | 9 ab | cde | f |
+ | - | --- | --- | | ----- | ---- | --- | - |
+ | N | 000 | BF2 | | 001.1 | 0 BF | BFA | M | mcrf
+
+16-bit only:
+
+ | 0 | 1234 | | 567.8 | 9 ab | cde | f |
+ | - | ---- | | ----- | ---- | --- | - |
+ | N | 0010 | | 001.1 | 0 BA | BB | M | crnor
+ | N | 0011 | | 001.1 | 0 BA | BB | M | crandc
+ | N | 0100 | | 001.1 | 0 BA | BB | M | crxor
+ | N | 0101 | | 001.1 | 0 BA | BB | M | crnand
+ | N | 0110 | | 001.1 | 0 BA | BB | M | crand
+ | N | 0111 | | 001.1 | 0 BA | BB | M | creqv
+ | N | 1000 | | 001.1 | 0 BA | BB | M | crorc
+ | N | 1001 | | 001.1 | 0 BA | BB | M | cror
+
+Notes
10 bit mode:
**not available** in 10-bit mode, **only** in 16-bit mode:
- | 0 1 2 3 | 4 | | 567.8 | 9 ab | cde | f |
- | ------- | - | | ----- | ---- | ---- | - |
- | 1 1 1 1 | 0 | | 001.1 | 0 00 | RT | M | mtlr
- | 1 1 1 1 | 0 | | 001.1 | 0 01 | RT | M | mtctr
- | 1 1 1 1 | 0 | | 001.1 | 0 11 | RT | M | mtcr
- | 1 1 1 1 | 1 | | 001.1 | 0 00 | RA | M | mflr
- | 1 1 1 1 | 1 | | 001.1 | 0 01 | RA | M | mfctr
- | 1 1 1 1 | 1 | | 001.1 | 0 11 | RA | M | mfcr
+ | 0 | 1 | 234 | | 567.8 | 9 ab | cde | f |
+ | - | ------- | | ----- | ---- | ---- | - |
+ | N | 1 | 111 | | 001.1 | 0 00 | RT | M | mtlr
+ | N | 1 | 111 | | 001.1 | 0 01 | RT | M | mtctr
+ | N | 1 | 111 | | 001.1 | 0 00 | RA | M | mflr
+ | N | 1 | 111 | | 001.1 | 0 01 | RA | M | mfctr
+ | N | 0 RA!=0 | | 000.0 | 0 00 | 000 | M | mtcr
+ | N | 1 RT!=0 | | 000.0 | 0 00 | 000 | M | mfcr
### Unallocated
- | 0 1 2 3 | 4 | | 567.8 | 9 ab | cde | f |
- | ------- | - | | ----- | ---- | ---- | - |
- | 0 1 0 1 | | | 001.1 | 0 | | M |
- | 1 0 1 0 | | | 001.1 | 0 | | M |
- | 1 0 1 1 | | | 001.1 | 0 | | M |
- | 1 1 0 0 | | | 001.1 | 0 | | M |
- | 1 1 1 1 | | | 001.1 | 0 10 | | M |
+16-bit only:
+
+ | 0 | 1 | 234 | | 567.8 | 9 ab | cde | f |
+ | - | - | --- | | ----- | ---- | ---- | - |
+ | N | 1 | 111 | | 001.1 | 0 10 | | M |
+ | N | 1 | 111 | | 001.1 | 0 11 | | M |
-## Other ideas (Attempt 2)
+# Other ideas (Attempt 2)
-### 8-bit mode-switching instructions, odd addresses for C mode
+## 8-bit mode-switching instructions, odd addresses for C mode
Drop the complexity of the 16-bit encoding further reduced to 10-bit,
and use a single byte instead of two to switch between modes. This
| .. bit | 16 bit | 8nop |
| v3.0B standard 32 bit instruction |
+# Other ideas (v3)
+
+FSM state switching and mode switching deemed too complex. Instead cut back to
+
+1. 10bit only (actually, 11 bit)
+2. SV-Prefixed 16bit only (aka SV-C32)
-### TODO
+Each will be entirely different which is a huge amount of work.
+
+# TODO
* make a preliminary assessment of branch in/out viability
* confirm FSM encoding (is LSB of PC really enough?)
objdump raw parsing
* finally do full opcode allocation
* rerun objdump compression ratio estimates
+* check in FSM if "return to v3.0B then 16bit" if it is ok to have the v3.0B be a 10bit Compressed. should this be ignored and carry on? should a trap occur?
### Use 2- rather than 3-register opcodes
forming a 32-bit operation, enabling us to remain in compressed mode
even longer.
-# Analysis techniques and tools
+# Appendix
+
+## Analysis techniques and tools
objdump -d --no-show-raw-insn /bin/bash | sed 'y/\t/ /;
s/^[ x0-9A-F]*: *\([a-z.]\+\) *\(.*\)/\1 \2 /p; d' |
s/\([ ,]\)-*[0-9]\+\([^0-9]\)/\11\2/g' | sort | uniq --count |
sort -n | less
-# gcc register allocation
+## gcc register allocation
FTR, information extracted from gcc's gcc/config/rs6000/rs6000.h about
fixed registers (assigned to special purposes) and register allocation
vrsave, vscr (fixed)
sfp (fixed)
-# Demo of encoding that's backward-compatible with PowerISA v3.1 in both LE and BE mode
+## Comparison to VLE
+
+VLE was a means to reduce executable size through three interleaved methods:
+
+* (1) invention of 16 bit encodings (of exactly 16 bit in length)
+* (2) invention of 16+16 bit encodings (a 16 bit instruction format but with
+ an *additional* 16 bit immediate "tacked on" to the end, actually
+ making a 32-bit instruction format)
+* (3) seamless and transparent embedding and intermingling of the
+ above in amongst arbitrary v2.06/7 BE 32 bit instruction sequences,
+ with no additional state,
+ including when the PC was not aligned on a 4-byte boundary.
+
+Whilst (1) and (3) make perfect sense, (2) makes no sense at all given that, as inspection of "ori" and others show, I-Form 16 bit immediates is the "norm" for v2.06/7 and v3.0B standard instructions. (2) in effect **is** a 32 bit instruction. (2) **is not** a 16 bit instruction.
+
+*Why "reinvent" an encoding that is 32 bit, when there already exists a 32 bit encoding that does the exact same job?*
+
+Consequently, we do **not** envisage a scenario where (2) would ever be implemented, nor in the future would this Compressed Encoding be extended beyond 16 bit. Compressed is Compressed and is **by definition** limited to precisely - and only - 16 bit.
+
+The additional reason why that is the case is because VLE is exceptionally complex to implement. In a single-issue, low clock rate "Embedded" environment for which VLE was originally designed, VLE was perfectly well matched.
+
+However this Compressed Encoding is designed for High performance multi-issue systems *as well* as Embedded scenarios, and consequently, the complexity of "deep packet inspection" down into the depths of a 16 bit sequence in order to ascertain if it might not be 16 bit after all, is wholly unacceptable.
+
+By eliminating such 16+16 (actually, 32bit conflation) tricks outlined in (2), Compressed is *specifically* designed to fit into a very small FSM, suitable for multi-issue, that in no way requires "deep-dive" analysis. Yet, despite it never being designed with 16 bit encodings in mind, is still suitable for retro-fitting onto OpenPOWER.
+
+## Compressed Decoder Phases
+
+Phase 1 (stage 1 of a 2-stage pipelined decoder) is defined as the minimum necessary FSM required to determine instruction length and mode. This is implemented with the absolute bare minimum of gates and is based on the 6 encodings involving N, M and EXTNNN (see table, below)
+
+Phase 2 (stage 2 of a 2-stage pipelined decoder) is defined as the "full decoder" that includes taking into account the length and mode from Phase 1. Given a 2-stage pipelined decoder it is categorically **impossible** for Phase 2 to go backwards in time and affect the decisions made in Phase 1.
+
+These two phases are specifically designed to take multi-issue execution into account. Phase 1 is intended to be part of an O(log N) algorithm that can use a form of carry-lookahead propagation. Phase 2 is intended to be on a 2nd pipelined clock cycle, comprising a separate suite of independent local-state-only parallel pipelines that do not require any inter-communication of any kind.
+
+Table: Reminder of the 6 16-bit encodings:
+
+ | 0 | 1234 | 567 8 | 9abcde | f | explanation
+ | - | ---- | ------ | ------ | - | -----------
+ | EXT000/1 | Cmaj.m | fields | 0 | 10bit then v3.0B
+ | EXT000/1 | Cmaj.m | fields | 1 | 10bit then 16bit
+ | 0 | flds | Cmaj.m | fields | 0 | 16bit then v3.0B
+ | 0 | flds | Cmaj.m | fields | 1 | 16bit then 16bit
+ | 1 | flds | Cmaj.m | fields | 0 | 16b, 1x v3.0B, 16b
+ | 1 | flds | Cmaj.m | fields | 1 | 16b/imm then 16bit
+
+### Phase 1
+
+The Phase 1 length/mode identification takes into account only 3 pieces of information:
+
+* extc_id: insn[0:4] == EXTNNN (Compressed)
+* N: insn[0]
+* M: insn[15]
+
+The Phase 1 length/mode produces the following lengths/modes:
+
+* 32 - v3.0B (includes v3.0B followed by 16bit)
+* 16 - 10bit
+* 16 - 16bit
+
+**NOTE THAT FURTHER SUBIDENTIFICATION OF C MODES IS NOT CARRIED OUT AT PHASE 1**. In particular note specifically that 16 bit "immediate mode" is **not** part of the Phase 1 FSM, but is specifically isolated to Phase 2.
+
+Pseudocode:
+
+ # starting point for FSM
+ previ = v3.0B
+
+ if previ.mode == v3.0B:
+ # previous was v3.0B, look for compressed tag
+ if extc_id:
+ # found it. move to 10bit mode
+ nexti.length = 16
+ nexti.mode = 10bit
+ else:
+ # nope. stay in v3.0B
+ nexti.length = 32
+ nexti.mode = v3.0B
+
+ elif previ.mode == 10bit:
+ # previous was v3.0B, move to v3.0B or 16bit?
+ if M == 0:
+ next.length = 32
+ nexti.mode = v3.0B
+ else:
+ # otherwise stay in 16bit mode
+ nexti.length = 16
+ nexti.mode = 16bit
+
+ elif previ.mode == 16bit:
+ # previous was 16bit, stay there or move?
+ if M == 0:
+ # back to v3.0B
+ next.length = 32
+ if N == 1:
+ # ... but only for 1 insn
+ nexti.mode = v3.0B_then_16bit
+ else:
+ nexti.mode = v3.0B
+ else:
+ # otherwise stay in 16bit mode
+ nexti.length = 16
+ nexti.mode = 16bit
+
+ # rest of FSM involving 3.0B to 16bit
+ # and back transitions left to implementor
+ # (or for someone else to add)
+
+### Phase 2: Compressed mode
+
+At this phase, knowing that the length is 16bit and the mode is either 10b or 16b, further analysis is required to determine if the 16bit.immediate encoding is active, and so on. This is a fully combinatorial block that **at no time** steps outside of the strict bounds already determined by Phase 1.
+
+ op_001_1 = insn[5:8] != 0b001.1
+ if mode == 10bit:
+ decode_10bit(insn)
+ elif mode == 16bit:
+ if N == 1 & M == 1 & op_001_1
+ # see immediate opcodes table
+ decode_16bit_immed_mode(insn)
+ if op_001_1:
+ # see CR and System tables
+ # (16 bit ones at least)
+ decode_16bit_cr_or_sys(insn)
+ else:
+ decode_16bit_nonimmed_mode(insn)
+
+From this point onwards each of the decode_xx functions perform straightforward combinatorial decoding of the 16 bits of "insn". In sone cases this involves further analysis of bit 1, in some cases (Cmaj.m = 0b010.1) even further deep-dive decoding is required (CR ops). *All* of it is entirely combinatorial and at **no time** involves changing of, or interaction with, or disruption of, the Phase 1 determination of Length+Mode (that has *already taken place* in an earlier decoding pipeline time-schedule)
+
+### Phase 2: v3.0B mode
+
+Standard v3.0B decoders are deployed. Absolutely no interaction occurs with any 16 bit decoders or state. Absolutely no interaction with the earlier Phase 1 decoding occurs. Absolutely no interaction occurs whatsoever (assuming an implementation that does not perform macro-op fusion) between other multi-issued v3.0B instructions being decoded in parallel at this time.
+
+## Demo of encoding that's backward-compatible with PowerISA v3.1 in both LE and BE mode
[[demo]]
-# Efficient Decoding Algorithm
+### Efficient Decoding Algorithm
[[decoding]]
projects / libreriscv.git / blobdiff