clarify cr 16-bit

[libreriscv.git] / openpower / sv / 16_bit_compressed.mdwn

diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn
index 17c372ce2be6fd76333b50b1aad6849c255239bc..5e3fc79e81d11b793b1673c0909d1b1ed3487515 100644 (file)
--- a/openpower/sv/16_bit_compressed.mdwn
+++ b/openpower/sv/16_bit_compressed.mdwn
@@ -81,9 +81,13 @@ The current "top" idea for 0b11 is to use it for a new encoding format
 of predominantly "immediates-based" 16-bit instructions (branch-conditional,
 addi, mulli etc.)
 
-The Compressed Major Opcode is in bits 5-7.
-
+* The Compressed Major Opcode is in bits 5-7.
+* Minor opcode in bit 8.
+* In some cases bit 9 is taken as an additional sub-opcode, followed
+  by bits 0-4 (for CR operations)
 * M+N mode-switching is not available for C-Major 0b001 or 0b111
+* 10 bit mode may be expanded by 16 bit mode, adding capabilities
+  that do not fit in the extreme limited space.
 
 ### Immediate Opcodes
 
@@ -104,13 +108,17 @@ only available in 16-bit mode, and only available when M=1 and N=1
 * Note that bc is included (below)
 * immediate is constructed from offs (LSBs) and o2 (MSB)
 * for LD/ST, offset is aligned.  8-byte: o2||offs||0b000 4-byte: 0b00
+* SV Prefix over-rides help provide alternative bitwidths for LD/ST
 * RB|0 if RB is zero, addi. becomes "li" (this only works if RT takes
   part of opcode).
 
 ### Branch
 
-10 bit mode may be expanded by 16 bit mode later, adding capabilities
-that do not fit in the extreme limited space.
+Note that illeg and nop are all zeros, including in the 16-bit mode.
+Given that C is allocated to OpenPOWER ISA Major opcodes EXT000 and
+EXT001 this ensures that in both 10-bit *and* 16-bit mode, a 16-bit
+run of all zeros is considered "illegal" whilst 0b0000.0000.1000.0000
+is "nop"
 
     | 16-bit mode | | 10-bit mode                 |
     | 0 | 1 | 234 | | 567.8  | 9  ab | c   de | f |
@@ -183,6 +191,8 @@ that do not fit in the extreme limited space.
 * for (RA|0) when RA=0 the input is a zero immediate,
   meaning that sub. becomes neg.
 * RT is implicitly RB: "add RT(=RB), RA, RB"
+* Opcode 0b010.0 RA=0 is not missing from the above:
+  it is a system-wide instruction, "cbank" (section below)
 
 ### Logical
 
@@ -266,7 +276,7 @@ Note here that elwidth overrides (SV Prefix) can be used to select FP16/32/64
 10 bit mode:
 
 * mcrf BF is only 2 bits which means the destination is only CR0-CR3
-* CR operations: **not available** in 10-bit mode
+* CR operations: **not available** in 10-bit mode (but mcrf is)
 
 16 bit mode:
 
@@ -286,8 +296,8 @@ Example: CBank=0b001 is heavily optimised to A/Video
 Encode/Decode.
 
     | 16-bit mode | | 10-bit mode               |
-    | 0 1 | 2 3 4 | | 567.8 | 9 a b | c d e | f |
-    |       Bank2 | | 010.0 | CBank | 0 0 0 | M | cbank
+    | 0 | 1 2 3 4 | | 567.8 | 9 a b | c d e | f |
+    | N |   Bank2 | | 010.0 | CBank | 0 0 0 | M | cbank
 
 **not available** in 10-bit mode: