(no commit message)

[libreriscv.git] / openpower / sv / biginteger.mdwn

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 1f7de4325ff2a02ab48f629a7f5c9613fafa8047..c84971b82731f7fadf7de77a34abcbef480c43df 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -49,19 +49,58 @@ fashion that is hidden from the user, behind a consistent, stable ISA API.
 The same macro-op fusion may theoretically be deployed even on Scalar
 operations.
 
-# dsld and dsrd
+# **DRAFT** dsld
 
-**DRAFT**
+|0.....5|6..10|11..15|16..20|21.25|26..30|31|
+|-------|-----|------|------|-----|------|--|
+| EXT04 | RT  |  RA  |  RB  | RC  |  XO  |Rc|
+
+VA2-Form
+
+* dsld    RT,RA,RB,RC  (Rc=0)
+* dsld.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), n)
+    mask <- MASK(0, 63-n)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
 
-`dsld` and `dsrd` are similar to v3.0 `sld`, and are VA2-Form
+# **DRAFT** dsrd
 
-|0.....5|6..10|11..15|16..20|21..25|26..30|31|
-|-------|-----|------|------|------|------|--|
-| EXT04 | RT  |  RA  |  RB  |   RC |  XO  |Rc|
+|0.....5|6..10|11..15|16..20|21.25|26..30|31|
+|-------|-----|------|------|-----|------|--|
+| EXT04 | RT  |  RA  |  RB  | RC  |  XO  |Rc|
+
+VA2-Form
+
+* dsrd    RT,RA,RB,RC  (Rc=0)
+* dsrd.   RT,RA,RB,RC  (Rc=1)
+
+Pseudo-code:
+
+    n <- (RB)[58:63]
+    v <- ROTL64((RA), 64-n)
+    mask <- MASK(n, 63)
+    RT <- (v[0:63] & mask) | ((RC) & ¬mask)
+    RS <- v[0:63] & ¬mask
+    overflow = 0
+    if RS != [0]*64:
+        overflow = 1
+
+Special Registers Altered:
+
+    CR0                    (if Rc=1)
 
-Both instructions take two 64-bit sources, concatenate
-them together then extract 64 bits from it, the offset
-location determined by a third source.
 
 # maddedu
 
@@ -176,11 +215,14 @@ Pseudo-code:
 
 For the Opcode map (XO Field)
 see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
-Proposed is the addition of `maddedu` (**DRAFT, NOT APPROVED**) in `110010`
-and `divmod2du` in `110100`
+Proposed is the addition of:
+
+* `maddedu` in `110010`
+* `divmod2du` in `111010`
+* `pcdec` in `111000`
 
-| v > |   000|   001 |   010    |   011|   100       |   101|   110|   111|
-|-----|------|-------|----------|------|-------------|------|------|------|
-| 110 |maddhd|maddhdu|**maddedu**|maddld|**divmod2du**|rsvd  |rsvd  |rsvd  |
-| 010 |dsld  |dsld.  |dsrd |dsrd. |mtvsrbmi |mtvsrbmi |vsldbi|vmsumcud|
+|v >|   000|   001 |   010    |   011|   100  |   101  |   110   |   111  |
+|---|------|-------|----------|------|--------|--------|---------|--------|
+|110|maddhd|maddhdu|maddedu   |maddld|rsvd    |rsvd    |rsvd     |rsvd    |
+|111|pcdec.|rsvd   |divmod2du |vpermr|vaddequm|vaddecuq|vsubeuqm |vsubecuq|