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[libreriscv.git] / openpower / sv / biginteger.mdwn

diff --git a/openpower/sv/biginteger.mdwn b/openpower/sv/biginteger.mdwn
index 2973944e1838cd7d631e90682b71f344248809a1..e92ba87d39df86bf393b06db1c84ad9fcf0596c0 100644 (file)
--- a/openpower/sv/biginteger.mdwn
+++ b/openpower/sv/biginteger.mdwn
@@ -34,7 +34,7 @@ Big-Divide.
 Macro-op Fusion and back-end massively-wide SIMD ALUs may be deployed in a
 fashion that is hidden from the user, behind a consistent, stable ISA API.
 
-# Instructions
+# madded
 
 **DRAFT**
 
@@ -44,15 +44,23 @@ fashion that is hidden from the user, behind a consistent, stable ISA API.
 |-------|-----|------|------|------|------|
 | EXT04 | RT  |  RA  |  RB  |   RC |  XO  |
 
-For the Opcode map (XO Field)
-see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
-Proposed is the addition of `msubed` (**DRAFT, NOT APPROVED**) which is
-in `110110`.  A corresponding `madded` is proposed for `110010`
+The pseudocode for `madded RT, RA, RB, RC` is:
+
+    prod[0:127] = (RA) * (RB)
+    sum[0:127] = EXTZ(RC) + prod
+    RT <- sum[64:127]
+    RS <- sum[0:63] # RS is either RC or RT+VL
 
-| 110000 | 110001  | 110010 | 110011 | 110100 | 110101 | 110110 | 110111 |
-| ------ | ------- | ------ | ------ | ------ | ------ | ------ | ------ |
-| maddhd | maddhdu | madded | maddld | rsvd   | rsvd   | rsvd   | rsvd   |
+RC is zero-extended (not shifted), the 128-bit product added
+to it; the lower half of that result stored in RT and the upper half
+in RS.
+
+The differences here to `maddhdu` are that `maddhdu` stores the upper
+half in RT, where `madded` stores the upper half in RS. There is no
+equivalent to `maddld` because `maddld` performs sign-extension on RC.
 
+As a Scalar Power ISA operation, like `lq` and `stq` RS=RT+1.
+SVP64 overrides this behaviour.
 For SVP64 EXTRA register extension, the `RM-1P-3S-1D` format is
 used with the additional bit set for determining RS.
 
@@ -62,7 +70,7 @@ used with the additional bit set for determining RS.
 | Rsrc1\_EXTRA2 | `12:13` | extends RA (R\*\_EXTRA2 Encoding)   |
 | Rsrc2\_EXTRA2 | `14:15` | extends RB (R\*\_EXTRA2 Encoding)   |
 | Rsrc3\_EXTRA2 | `16:17` | extends RC (R\*\_EXTRA2 Encoding)   |
-| EXTRA2_MODE   | `18`    | used by `msubed` and `madded` for RS   |
+| EXTRA2_MODE   | `18`    | used by `madded` for determining RS |
 
 When `EXTRA2_MODE` is set to zero, the implicit RS register takes
 its Vector/Scalar setting from Rdest_EXTRA2, and takes
@@ -74,20 +82,52 @@ When `EXTRA2_MODE` is set to one, the implicit RS register is identical
 to RC extended to SVP64 numbering, including whether RC is set Scalar or
 Vector.
 
-## madded
+# divrem2du RT,RA,RB,RC
 
-The pseudocode for `madded RT, RA, RB, RC` is:
+**DRAFT**
 
-    prod[0:127] = (RA) * (RB)
-    sum[0:127] = EXTZ(RC) + prod
-    RT <- sum[64:127]
-    RS <- sum[0:63] # RS is either RC or RT+VL
+Divide/Modulu Quad-Double Unsigned is another VA-Form instruction
+that is near-identical to `divdeu` except that:
 
-Again RC is zero-extended (not shifted), the 128-bit product added
-to it; the lower half of the result stored in RT and the upper half
-in RS.
+* the lower 64 bits of the dividend, instead of being zero, contain a
+  register, RC.
+* it performs a fused divide and modulo in a single instruction, storing
+  the modulo in an implicit RS (similar to `madded`)
 
-The differences here to `maddhdu` are that `maddhdu` stores the upper
-half in RT, where `madded` stores the upper half in RS. There is no
-equivalent to `maddld` because `maddld` performs sign-extension on RC.
+RB, the divisor, remains 64 bit.  The instruction is therefore a 128/64
+division, producing a (pair) of 64 bit result(s).  Overflow conditions
+are detected in exactly the same fashion as `divdeu`, except that rather
+than have `UNDEFINED` behaviour, RT is set to all ones and RS set to all
+zeros.
+
+For SVP64, given that this instruction is also 3-in 2-out 64-bit registers,
+the exact same EXTRA format and setting of RS is used as for `sv.madded`.
+For Scalar usage, just as for `madded`, `RS=RT+1` (similar to `lq` and `stq`).
+
+Pseudo-code:
+
+    if ((RA) <u (RB)) & ((RB) != [0]*XLEN) then
+        dividend[0:(XLEN*2)-1] <- (RA) || (RC)
+        divisor[0:(XLEN*2)-1] <- [0]*XLEN || (RB)
+        result <- dividend / divisor
+        modulo <- dividend % divisor
+        RT <- result[XLEN:(XLEN*2)-1]
+        RS <- modulo[XLEN:(XLEN*2)-1]
+        overflow <- 0
+    else
+        overflow <- 1
+        RT <- [1]*XLEN
+        RS <- [0]*XLEN
+
+
+# [DRAFT] EXT04 Proposed Map
+
+For the Opcode map (XO Field)
+see Power ISA v3.1, Book III, Appendix D, Table 13 (sheet 7 of 8), p1357.
+Proposed is the addition of `madded` (**DRAFT, NOT APPROVED**) in `110010`
+and `divrem2du` in `110100`
+
+|110000|110001 |110010    |110011|110100       |110101|110110|110111|
+|------|-------|----------|------|-------------|------|------|------|
+|maddhd|maddhdu|**madded**|maddld|**divrem2du**|rsvd  |rsvd  |rsvd  |