this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
Vectorisation Context is provided by [[openpower/sv]].
-Scaoar variants of bitmanip oerations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, because VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
+When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
-ternaryv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternary operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve a similar objective.
+ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
-general-purpose Galois Field operations are added so as to avoid huge opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
+general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
-note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]],
-the [[sv/av_opcodes]] and [[sv/cr_int_predication]]
+note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
+the [[sv/av_opcodes]] as well as [[sv/setvl]]
+
+Useful resource:
+
+* <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
+* <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
# summary
| 28.30 |31| name |
| ------ |--| --------- |
- | 00 |Rc| ternaryi |
- | 001 |Rc| ternary |
+ | 00 |Rc| ternlogi |
+ | 001 |Rc| ternlog |
| 010 |Rc| bitmask |
| 011 |Rc| gf* |
- | 101 |1 | ternaryv |
- | 101 |0 | ternarycr |
+ | 101 |1 | ternlogv |
+ | 101 |0 | ternlogcr |
| 110 |Rc| 1/2-op |
| 111 |Rc| 3-op |
| ---- | ---- | ---- | ----- | -------- |
| RT | RA | RB | or | bmatflip |
| RT | RA | RB | xor | bmatflip |
-| RT | RA | RB | bdep | dep/ext |
-| RT | RA | RB | bext | dep/ext |
| RT | RA | RB | | grev |
| RT | RA | RB | | clmul* |
| RT | RA | RB | | gorc |
| RT | RA | RB | unshuf| shuffle |
| RT | RA | RB | width | xperm |
| RT | RA | RB | type | minmax |
-| RT | RA | RB | | |
-| RT | RA | RB | | |
+| RT | RA | RB | | av abs avgadd |
+| RT | RA | RB | type | vmask ops |
| RT | RA | RB | | |
3 ops
* bitmask set/extract
-* ternary bitops
+* ternlog bitops
* GF
| 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
| -- | -- | --- | --- | ----- | -------- |--| ------ |
-| NN | RT | RA | RB | RC | mode 001 |Rc| ternary |
-| NN | RT | RA | RB | im0-4 | im5-7 00 |Rc| ternaryi |
+| NN | RT | RA | RB | RC | mode 001 |Rc| ternlog |
+| NN | RT | RA | RB | im0-4 | im5-7 00 |Rc| ternlogi |
| NN | RS | RA | RB | RC | 00 011 |Rc| gfmul |
| NN | RS | RA | RB | RC | 01 011 |Rc| gfadd |
| NN | RT | RA | RB | deg | 10 011 |Rc| gfinv |
| 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
| -- | -- | --- | ----- | ---- | ----- |--| ------ |
-| NN | RT | RA | imm | mask | 101 |1 | ternaryv |
+| NN | RT | RA | imm | mask | 101 |1 | ternlogv |
| 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
| -- | -- | --- | --- |- |-----|----- | -----|--| -------|
-| NN | BA | BB | BC |0 |imm | mask | 101 |0 | ternarycr |
+| NN | BA | BB | BC |0 |imm | mask | 101 |0 | ternlogcr |
-ops
+ops (note that av avg and abs as well as vec scalar mask
+are included here)
| 0.5|6.10|11.15|16.20| 21.22 | 23 | 24....30 |31| name |
| -- | -- | --- | --- | ----- | -- | -------- |--| ---- |
| NN | RA | RB | | | 0 | 0000 110 |Rc| rsvd |
| NN | RA | RB | RC | itype | 1 | 0000 110 |Rc| xperm |
| NN | RA | RB | RC | itype | 0 | 0100 110 |Rc| minmax |
-| NN | RA | RB | | | 1 | 0100 110 |Rc| rsvd |
+| NN | RA | RB | RC | 00 | 1 | 0100 110 |Rc| av avgadd |
+| NN | RA | RB | RC | 01 | 1 | 0100 110 |Rc| av abs |
+| NN | RA | RB | | 10 | 1 | 0100 110 |Rc| rsvd |
+| NN | RA | RB | | 11 | 1 | 0100 110 |Rc| rsvd |
| NN | RA | RB | sh | itype | SH | 1000 110 |Rc| bmopsi |
| NN | RA | RB | | | | 1100 110 |Rc| rsvd |
-| NN | RA | RB | | | | 1100 110 |Rc| rsvd |
-| NN | RA | RB | | | | 1100 110 |Rc| rsvd |
-| NN | RA | RB | | | | 1100 110 |Rc| rsvd |
-| NN | RA | RB | | | 0 | 0001 110 |Rc| rsvd |
+| NN | RA | RB | | | 1 | 0001 110 |Rc| rsvd |
+| NN | RA | RB | RC | 00 | 0 | 0001 110 |Rc| vec sbfm |
+| NN | RA | RB | RC | 01 | 0 | 0001 110 |Rc| vec sofm |
+| NN | RA | RB | RC | 10 | 0 | 0001 110 |Rc| vec sifm |
+| NN | RA | RB | RC | 11 | 0 | 0001 110 |Rc| vec cprop |
| NN | RA | RB | | | 0 | 0101 110 |Rc| rsvd |
| NN | RA | RB | RC | 00 | 0 | 0010 110 |Rc| gorc |
| NN | RA | RB | sh | 00 | SH | 1010 110 |Rc| gorci |
| NN | RA | RB | RC | 10 | 0 | 0010 110 |Rc| shfl |
| NN | RA | RB | sh | 10 | SH | 1010 110 |Rc| shfli |
| NN | RA | RB | RC | 10 | 0 | 0110 110 |Rc| shflw |
-| NN | RA | RB | RC | 10 | 0 | 1110 110 |Rc| bdep |
-| NN | RA | RB | RC | 10 | 1 | 1110 110 |Rc| bext |
+| NN | RA | RB | RC | 10 | | 1110 110 |Rc| rsvd |
| NN | RA | RB | RC | 11 | 0 | 1110 110 |Rc| clmulr |
| NN | RA | RB | RC | 11 | 1 | 1110 110 |Rc| clmulh |
-| NN | RA | RB | | | | NN11 110 |Rc| rsvd |
+| NN | | | | | | --11 110 |Rc| setvl |
# count leading/trailing zeros with mask
# centrifuge
-found in v3.1 p106
+found in v3.1 p106 so not to be added here
```
ptr0 = 0
```
-# ternary bitops
+# ternlog bitops
-Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register
+Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
+
+Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
| 0.5|6.10|11.15|16.20| 21..25| 26..30 |31|
| -- | -- | --- | --- | ----- | -------- |--|
bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate. for the immediate version this does not matter, so a bmexti is not required.
bmrev however there is no direct equivalent and consequently a bmrevi is required.
+bmset (register for mask amount) is particularly useful for creating
+predicate masks where the length is a dynamic runtime quantity.
+bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
+
| 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
| -- | -- | --- | --- | --- | ------- |--| ----- |
| NN | RT | RA | RB | RC | mode 010 |Rc| bm* |
# cmix
-based on RV bitmanip, covered by ternary bitops
+based on RV bitmanip, covered by ternlog bitops
```
uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
projects / libreriscv.git / blobdiff