* ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
* grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
* GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
-
+* binutils <https://bugs.libre-soc.org/show_bug.cgi?id=836>
+* shift-and-add <https://bugs.libre-soc.org/show_bug.cgi?id=968>
# bitmanipulation
pseudocode: [[openpower/isa/bitmanip]]
-this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
-Also included are DSP/Multimedia operations suitable for
-Audio/Video. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
-Vectorisation Context is provided by [[openpower/sv]].
-
-When combined with SV, scalar variants of bitmanip operations found in VSX are added so that the Packed SIMD aspects of VSX may be retired as "legacy"
-in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
-
-ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
-
-general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
-
-note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
-the [[sv/av_opcodes]] as well as [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
+this extension amalgamates bitmanipulation primitives from many sources,
+including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
+Also included are DSP/Multimedia operations suitable for Audio/Video.
+Vectorization and SIMD are removed: these are straight scalar (element)
+operations making them suitable for embedded applications. Vectorization
+Context is provided by [[openpower/sv]].
+
+When combined with SV, scalar variants of bitmanip operations found in
+VSX are added so that the Packed SIMD aspects of VSX may be retired as
+"legacy" in the far future (10 to 20 years). Also, VSX is hundreds of
+opcodes, requires 128 bit pathways, and is wholly unsuited to low power
+or embedded scenarios.
+
+ternlogv is experimental and is the only operation that may be considered
+a "Packed SIMD". It is added as a variant of the already well-justified
+ternlog operation (done in AVX512 as an immediate only) "because it
+looks fun". As it is based on the LUT4 concept it will allow accelerated
+emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to
+achieve similar objectives.
+
+general-purpose Galois Field 2^M operations are added so as to avoid
+huge custom opcode proliferation across many areas of Computer Science.
+however for convenience and also to avoid setup costs, some of the more
+common operations (clmul, crc32) are also added. The expectation is
+that these operations would all be covered by the same pipeline.
+
+note that there are brownfield spaces below that could incorporate
+some of the set-before-first and other scalar operations listed in
+[[sv/mv.swizzle]],
+[[sv/vector_ops]], [[sv/int_fp_mv]] and the [[sv/av_opcodes]] as well as
+[[sv/setvl]], [[sv/svstep]], [[sv/remap]]
Useful resource:
* <https://en.wikiversity.org/wiki/Reed%E2%80%93Solomon_codes_for_coders>
* <https://maths-people.anu.edu.au/~brent/pd/rpb232tr.pdf>
+* <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
+* <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
-# summary
-
-two major opcodes are needed
-
-ternlog has its own major opcode
-
-| 29.30 |31| name |
-| ------ |--| --------- |
-| 0 0 |Rc| ternlogi |
-| 0 1 | | rsvd |
-| 1 iv | | grevlogi |
-
-2nd major opcode for other bitmanip: minor opcode allocation
-
-| 28.30 |31| name |
-| ------ |--| --------- |
-| -00 |0 | xpermi |
-| -00 |1 | grevlog |
-| -01 | | crternlog |
-| 010 |Rc| bitmask |
-| 011 | | SVP64 |
-| 110 |Rc| 1/2-op |
-| 111 | | bmrevi |
-
-
-1-op and variants
-
-| dest | src1 | subop | op |
-| ---- | ---- | ----- | -------- |
-| RT | RA | .. | bmatflip |
-
-2-op and variants
-
-| dest | src1 | src2 | subop | op |
-| ---- | ---- | ---- | ----- | -------- |
-| RT | RA | RB | or | bmatflip |
-| RT | RA | RB | xor | bmatflip |
-| RT | RA | RB | | grev |
-| RT | RA | RB | | clmul\* |
-| RT | RA | RB | | gorc |
-| RT | RA | RB | shuf | shuffle |
-| RT | RA | RB | unshuf| shuffle |
-| RT | RA | RB | width | xperm |
-| RT | RA | RB | type | av minmax |
-| RT | RA | RB | | av abs avgadd |
-| RT | RA | RB | type | vmask ops |
-| RT | RA | RB | type | abs accumulate (overwrite) |
-
-3 ops
-
-* grevlog
-* GF mul-add
-* bitmask-reverse
-
-TODO: convert all instructions to use RT and not RS
-
-| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
-| -- | -- | --- | --- | ----- | -------- |--| ------ |
-| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi |
-| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
-| NN | | | | | ----- 01 |m3| crternlogi |
-| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask\* |
-| NN | RT | RA | RB | RC | 00 011 |nh| binlut |
-| NN | | | | | 01 011 |0 | svshape |
-| NN | | | | | 01 011 |1 | svremap |
-| NN | | | | | 10 011 |Rc| svstep |
-| NN | | | | | 11 011 |Rc| setvl |
-| NN | | | | | ---- 110 | | 1/2 ops |
-| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi |
-
-ops (note that av avg and abs as well as vec scalar mask
-are included here [[sv/vector_ops]], and
-the [[sv/av_opcodes]])
-
-TODO: convert from RA, RB, and RC to correct field names of RT, RA, and RB, and
-double check that instructions didn't need 3 inputs.
-
-| 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
-| -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
-| NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi | {TODO} |
-| NN | RS | RA | sh | SH | 0 1 | nn00 110 |Rc| bmopsi | XB-Form |
-| NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv | X-Form |
-| NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod | X-Form |
-| NN | RT | RA | | 1 | 10 | 0001 110 |Rc| bmatflip | X-Form |
-| NN | | | | 1 | 11 | 0001 110 |Rc| rsvd | |
-| NN | RT | RA | RB | 0 | 00 | 0001 110 |Rc| vec sbfm | X-Form |
-| NN | RT | RA | RB | 0 | 01 | 0001 110 |Rc| vec sofm | X-Form |
-| NN | RT | RA | RB | 0 | 10 | 0001 110 |Rc| vec sifm | X-Form |
-| NN | RT | RA | RB | 0 | 11 | 0001 110 |Rc| vec cprop | X-Form |
-| NN | | | | | -0 | 0101 110 |Rc| crbinlog | {TODO} |
-| NN | | | | | -1 | 0101 110 |Rc| rsvd | |
-| NN | RT | RA | RB | 0 | itype | 1001 110 |Rc| av minmax | X-Form |
-| NN | RT | RA | RB | 1 | 00 | 1001 110 |Rc| av abss | X-Form |
-| NN | RT | RA | RB | 1 | 01 | 1001 110 |Rc| av absu | X-Form |
-| NN | RT | RA | RB | 1 | 10 | 1001 110 |Rc| av avgadd | X-Form |
-| NN | | | | 1 | 11 | 1001 110 |Rc| rsvd | |
-| NN | RT | RA | RB | 0 | itype | 1101 110 |Rc| shadd | {TODO} |
-| NN | RT | RA | RB | 1 | itype | 1101 110 |Rc| shadduw | {TODO} |
-| NN | RT | RA | RB | 0 | 00 | 0010 110 |Rc| gorc | X-Form |
-| NN | RS | RA | sh | SH | 00 | 1010 110 |Rc| gorci | XB-Form |
-| NN | RT | RA | RB | 0 | 00 | 0110 110 |Rc| gorcw | X-Form |
-| NN | RS | RA | SH | 0 | 00 | 1110 110 |Rc| gorcwi | X-Form |
-| NN | RT | RA | RB | 1 | 00 | 1110 110 |Rc| bmator | X-Form |
-| NN | RT | RA | RB | 0 | 01 | 0010 110 |Rc| grev | X-Form |
-| NN | RT | RA | RB | 1 | 01 | 0010 110 |Rc| clmul | X-Form |
-| NN | RS | RA | sh | SH | 01 | 1010 110 |Rc| grevi | XB-Form |
-| NN | RT | RA | RB | 0 | 01 | 0110 110 |Rc| grevw | X-Form |
-| NN | RS | RA | SH | 0 | 01 | 1110 110 |Rc| grevwi | X-Form |
-| NN | RT | RA | RB | 1 | 01 | 1110 110 |Rc| bmatxor | X-Form |
-| NN | RS | RA | RB | 0 | 10 | 0010 110 |Rc| abssa | X-Form |
-| NN | RS | RA | RB | 0 | 10 | 0110 110 |Rc| absua | X-Form |
-| NN | RS | RA | RB | 0 | 10 | 1010 110 |Rc| | X-Form |
-| NN | RS | RA | RB | 0 | 10 | 1110 110 |Rc| | X-Form |
-| NN | RT | RA | RB | 1 | 10 | 0010 110 |Rc| xpermn | |
-| NN | RT | RA | RB | 1 | 10 | 0110 110 |Rc| xpermb | |
-| NN | RT | RA | RB | 1 | 10 | 1010 110 |Rc| xpermh | |
-| NN | RT | RA | RB | 1 | 10 | 1110 110 |Rc| xpermw | |
-| NN | RT | RA | RB | 0 | 11 | 1110 110 |Rc| clmulr | X-Form |
-| NN | RT | RA | RB | 1 | 11 | 1110 110 |Rc| clmulh | X-Form |
-| NN | | | | | | --11 110 |Rc| rsvd | |
+[[!inline pages="openpower/sv/draft_opcode_tables" quick="yes" raw="yes" ]]
# binary and ternary bitops
-Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
+Similar to FPGA LUTs: for two (binary) or three (ternary) inputs take
+bits from each input, concatenate them and perform a lookup into a
+table using an 8-8-bit immediate (for the ternary instructions), or in
+another register (4-bit for the binary instructions). The binary lookup
+instructions have CR Field lookup variants due to CR Fields being 4 bit.
-Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
+Like the x86 AVX512F
+[vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq)
+instructions.
## ternlogi
lookup table is 4 bits wide not 8 bits, and secondly the lookup
table comes from a register not an immediate.
-| 0.5|6.10|11.15|16.20| 21..25|26..30|31|
-| -- | -- | --- | --- | ----- | ---- |--|
-| NN | RT | RA | RB | RC |00011 |nh|
+| 0.5|6.10|11.15|16.20| 21..25|26..31 | Form |
+| -- | -- | --- | --- | ----- |--------|---------|
+| NN | RT | RA | RB | RC |nh 00001| VA-Form |
+| NN | RT | RA | RB | /BFA/ |0 01001| VA-Form |
+
+For binlut, the 4-bit LUT may be selected from either the high nibble
+or the low nibble of the first byte of RC:
lut2(imm, a, b):
idx = b << 1 | a
for i in range(64):
RT[i] = lut2(imm, RB[i], RA[i])
+For bincrlut, `BFA` selects the 4-bit CR Field as the LUT2:
+
+ for i in range(64):
+ RT[i] = lut2(CRs{BFA}, RB[i], RA[i])
+
+When Vectorized with SVP64, as usual both source and destination may be
+Vector or Scalar.
+
*Programmer's note: a dynamic ternary lookup may be synthesised from
a pair of `binlut` instructions followed by a `ternlogi` to select which
to merge. Use `nh` to select which nibble to use as the lookup table
-from the RC source register (`nh=1` nibble high)*
+from the RC source register (`nh=1` nibble high), i.e. keeping
+an 8-bit LUT3 in RC, the first `binlut` instruction may set nh=0 and
+the second nh=1.*
## crternlogi
-another mode selection would be CRs not Ints.
+another mode selection would be CRs not Ints.
+
+CRB-Form:
-| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
-| -- | -- | --- | --- | --- |-----|----- | -----|--|
-| NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
+| 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
+|----|----|----|-----|-----|-----|-----|-----|---|
+| NN | BF | msk|BFA | msk | BFB | TLI | XO |TLI|
- mask = m0-3,m4
for i in range(4):
- a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
- if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
+ a,b,c = CRs[BF][i], CRs[BFA][i], CRs[BFB][i])
+ if msk[i] CRs[BF][i] = lut3(imm, a, b, c)
+
+This instruction is remarkably similar to the existing crops, `crand` etc.
+which have been noted to be a 4-bit (binary) LUT. In effect `crternlogi`
+is the ternary LUT version of crops, having an 8-bit LUT. However it
+is an overwrite instruction in order to save on register file ports,
+due to the mask requiring the contents of the BF to be both read and
+written.
+
+Programmer's note: This instruction is useful when combined with Matrix REMAP
+in "Inner Product" Mode, creating Warshall Transitive Closure that has many
+applications in Computer Science.
## crbinlog
-| 0.5|6.8 | 9.11|12.14|15.17|18.22|23...30 |31|
-| -- | -- | --- | --- | --- |-----| --------|--|
-| NN | BT | BA | BB | BC |m0-m2|00101110 |m3|
+With ternary (LUT3) dynamic instructions being very costly,
+and CR Fields being only 4 bit, a binary (LUT2) variant is better
+
+CRB-Form:
+
+| 0.5|6.8 |9.10|11.13|14.15|16.18|19.25|26.30| 31|
+|----|----|----|-----|-----|-----|-----|-----|---|
+| NN | BF | msk|BFA | msk | BFB | // | XO | //|
- mask = m0-3,m4
for i in range(4):
- a,b = CRs[BA][i], CRs[BB][i])
- if mask[i] CRs[BT][i] = lut2(CRs[BC], a, b)
+ a,b = CRs[BF][i], CRs[BF][i])
+ if msk[i] CRs[BF][i] = lut2(CRs[BFB], a, b)
+
+When SVP64 Vectorized any of the 4 operands may be Scalar or
+Vector, including `BFB` meaning that multiple different dynamic
+lookups may be performed with a single instruction. Note that
+this instruction is deliberately an overwrite in order to reduce
+the number of register file ports required: like `crternlogi`
+the contents of `BF` **must** be read due to the mask only
+writing back to non-masked-out bits of `BF`.
+
+*Programmer's note: just as with binlut and ternlogi, a pair
+ of crbinlog instructions followed by a merging crternlogi may
+ be deployed to synthesise dynamic ternary (LUT3) CR Field
+ manipulation*
# int ops
required for the [[sv/av_opcodes]]
-signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
+signed and unsigned min/max for integer.
signed/unsigned min/max gives more flexibility.
+\[un]signed min/max instructions are specifically needed for vector reduce min/max operations which are pretty common.
+
+X-Form
+
+* PO=19, XO=----000011 `minmax RT, RA, RB, MMM`
+* PO=19, XO=----000011 `minmax. RT, RA, RB, MMM`
+
+see [[openpower/sv/rfc/ls013]] for `MMM` definition and pseudo-code.
+
+implements all of (and more):
+
```
-uint_xlen_t min(uint_xlen_t rs1, uint_xlen_t rs2)
+uint_xlen_t mins(uint_xlen_t rs1, uint_xlen_t rs2)
{ return (int_xlen_t)rs1 < (int_xlen_t)rs2 ? rs1 : rs2;
}
-uint_xlen_t max(uint_xlen_t rs1, uint_xlen_t rs2)
+uint_xlen_t maxs(uint_xlen_t rs1, uint_xlen_t rs2)
{ return (int_xlen_t)rs1 > (int_xlen_t)rs2 ? rs1 : rs2;
}
uint_xlen_t minu(uint_xlen_t rs1, uint_xlen_t rs2)
}
```
-## abs
+## absdu
required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
but not scalar
```
-uint_xlen_t intabs(uint_xlen_t rs1, uint_xlen_t rs2) {
+uint_xlen_t absdu(uint_xlen_t rs1, uint_xlen_t rs2) {
return (src1 > src2) ? (src1-src2) : (src2-src1)
}
```
SVP64 designation from RS-as-dest. This gives a limited range of
non-overwrite capability.
-# shift-and-add
+# shift-and-add <a name="shift-add"> </a>
Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
Too complex to add more LD/ST, a compromise is to add shift-and-add.
Replaces a pair of explicit instructions in hot-loops.
```
-uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
- return (rs1 << (sh+1)) + rs2;
-}
-
-uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
- uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
- return (rs1z << (sh+1)) + rs2;
-}
+# 1.6.27 Z23-FORM
+ |0 |6 |11 |15 |16 |21 |23 |31 |
+ | PO | RT | RA | RB |sm | XO |Rc |
```
-# cmix
+Pseudo-code (shadd):
-based on RV bitmanip, covered by ternlog bitops
+ n <- (RB)
+ m <- sm + 1
+ RT <- (n[m:XLEN-1] || [0]*m) + (RA)
+
+Pseudo-code (shaddw):
+
+ shift <- sm + 1 # Shift is between 1-4
+ n <- EXTS((RB)[XLEN/2:XLEN-1]) # Only use lower XLEN/2-bits of RB
+ RT <- (n << shift) + (RA) # Shift n, add RA
+
+Pseudo-code (shadduw):
+
+ n <- ([0]*(XLEN/2)) || (RB)[XLEN/2:XLEN-1]
+ m <- sm + 1
+ RT <- (n[m:XLEN-1] || [0]*m) + (RA)
```
-uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
- return (RA & RB) | (RC & ~RB);
+uint_xlen_t shadd(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
+ sm = sm & 0x3;
+ return (RB << (sm+1)) + RA;
}
-```
+uint_xlen_t shaddw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
+ uint_xlen_t n = (int_xlen_t)(RB << XLEN / 2) >> XLEN / 2;
+ sm = sm & 0x3;
+ return (n << (sm+1)) + RA;
+}
+
+uint_xlen_t shadduw(uint_xlen_t RA, uint_xlen_t RB, uint8_t sm) {
+ uint_xlen_t n = RB & 0xFFFFFFFF;
+ sm = sm & 0x3;
+ return (n << (sm+1)) + RA;
+}
+```
# bitmask set
based on RV bitmanip singlebit set, instruction format similar to shift
-[[isa/fixedshift]]. bmext is actually covered already (shift-with-mask rldicl but only immediate version).
-however bitmask-invert is not, and set/clr are not covered, although they can use the same Shift ALU.
+[[isa/fixedshift]]. bmext is actually covered already (shift-with-mask
+rldicl but only immediate version). however bitmask-invert is not,
+and set/clr are not covered, although they can use the same Shift ALU.
-bmext (RB) version is not the same as rldicl because bmext is a right shift by RC, where rldicl is a left rotate. for the immediate version this does not matter, so a bmexti is not required.
-bmrev however there is no direct equivalent and consequently a bmrevi is required.
+bmext (RB) version is not the same as rldicl because bmext is a right
+shift by RC, where rldicl is a left rotate. for the immediate version
+this does not matter, so a bmexti is not required. bmrev however there
+is no direct equivalent and consequently a bmrevi is required.
bmset (register for mask amount) is particularly useful for creating
predicate masks where the length is a dynamic runtime quantity.
-bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask" in a single instruction without needing to initialise or depend on any other registers.
+bmset(RA=0, RB=0, RC=mask) will produce a run of ones of length "mask"
+in a single instruction without needing to initialise or depend on any
+other registers.
| 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
| -- | -- | --- | --- | --- | ------- |--| ----- |
}
```
-bitmask extract with reverse. can be done by bit-order-inverting all of RB and getting bits of RB from the opposite end.
+bitmask extract with reverse. can be done by bit-order-inverting all
+of RB and getting bits of RB from the opposite end.
when RA is zero, no shift occurs. this makes bmextrev useful for
simply reversing all bits of a register.
rev[0:msb] = rb[msb:0];
rt = ZE(rev[msb:0]);
-uint_xlen_t bmextrev(RA, RB, sh)
+uint_xlen_t bmrevi(RA, RB, sh)
{
int shamt = XLEN-1;
if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
shamt = (XLEN-1)-shamt; # shift other end
- bra = bitreverse(RB) # swap LSB-MSB
+ brb = bitreverse(GPR(RB)) # swap LSB-MSB
mask = (2<<sh)-1;
- return mask & (bra >> shamt);
+ return mask & (brb >> shamt);
+}
+
+uint_xlen_t bmrev(RA, RB, RC) {
+ return bmrevi(RA, RB, GPR(RC) & 0b111111);
}
```
-| 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name |
-| -- | -- | --- | --- | --- | ------- |--| ------ |
-| NN | RT | RA | RB | sh | 1 011 |Rc| bmrevi |
+| 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name | Form |
+| -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
+| NN | RT | RA | RB | sh | 1111 |Rc| bmrevi | MDS-Form |
+| 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name | Form |
+| -- | -- | --- | --- | --- | ------- |--| ------ | -------- |
+| NN | RT | RA | RB | RC | 11110 |Rc| bmrev | VA2-Form |
-# grevlut
+# grevlut <a name="grevlut"> </a>
generalised reverse combined with a pair of LUT2s and allowing
a constant `0b0101...0101` when RA=0, and an option to invert
grevlut should be arranged so as to produce the constants
needed to put into bext (bitextract) so as in turn to
-be able to emulate x86 pmovmask instructions <https://www.felixcloutier.com/x86/pmovmskb>.
+be able to emulate x86 pmovmask instructions
+<https://www.felixcloutier.com/x86/pmovmskb>.
This only requires 2 instructions (grevlut, bext).
Note that if the mask is required to be placed
The following settings provide the required mask constants:
-| RA | RB | imm | iv | result |
+| RA=0 | RB | imm | iv | result |
| ------- | ------- | ---------- | -- | ---------- |
| 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
| 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
demo code [[openpower/sv/grevlut.py]]
```
-lut2(imm, a, b):
+def lut2(imm, a, b):
idx = b << 1 | a
- return imm[idx] # idx by LSB0 order
-
-dorow(imm8, step_i, chunksize):
- for j in 0 to 63:
- if (j&chunk_size) == 0
- imm = imm8[0..3]
- else
- imm = imm8[4..7]
- step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
+ return (imm>>idx) & 1
+
+def dorow(imm8, step_i, chunk_size):
+ step_o = 0
+ for j in range(64):
+ if (j&chunk_size) == 0:
+ imm = (imm8 & 0b1111)
+ else:
+ imm = (imm8>>4)
+ a = (step_i>>j)&1
+ b = (step_i>>(j ^ chunk_size))&1
+ res = lut2(imm, a, b)
+ #print(j, bin(imm), a, b, res)
+ step_o |= (res<<j)
+ #print (" ", chunk_size, bin(step_o))
return step_o
-uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 imm, bool iv)
-{
- uint64_t x = 0x5555_5555_5555_5555;
- if (RA != 0) x = GPR(RA);
- if (iv) x = ~x;
- int shamt = RB & 63;
- for i in 0 to 6
+def grevlut64(RA, RB, imm, iv):
+ x = 0
+ if RA is None: # RA=0
+ x = 0x5555555555555555
+ else:
+ x = RA
+ if (iv): x = ~x;
+ shamt = RB & 63;
+ for i in range(6):
step = 1<<i
- if (shamt & step) x = dorow(imm, x, step)
- return x;
-}
-
+ if (shamt & step):
+ x = dorow(imm, x, step)
+ return x & ((1<<64)-1)
```
-| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
-| -- | -- | --- | --- | ----- | -------- |--| ------ |
-| NN | RT | RA | s0-4 | im0-4 | im5-7 1 iv |s5| grevlogi |
-| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
-
-
-# grev
-
-superceded by grevlut
-
-based on RV bitmanip, this is also known as a butterfly network. however
-where a butterfly network allows setting of every crossbar setting in
-every row and every column, generalised-reverse (grev) only allows
-a per-row decision: every entry in the same row must either switch or
-not-switch.
-
-<img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
+A variant may specify different LUT-pairs per row,
+using one byte of RB for each. If it is desired that
+a particular row-crossover shall not be applied it is
+a simple matter to set the appropriate LUT-pair in RB
+to effect an identity transform for that row (`0b11001010`).
```
-uint64_t grev64(uint64_t RA, uint64_t RB)
+uint64_t grevlutr(uint64_t RA, uint64_t RB, bool iv, bool is32b)
{
- uint64_t x = RA;
- int shamt = RB & 63;
- if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
- ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
- if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
- ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
- if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
- ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
- if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
- ((x & 0xFF00FF00FF00FF00LL) >> 8);
- if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
- ((x & 0xFFFF0000FFFF0000LL) >> 16);
- if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
- ((x & 0xFFFFFFFF00000000LL) >> 32);
+ uint64_t x = 0x5555_5555_5555_5555;
+ if (RA != 0) x = GPR(RA);
+ if (iv) x = ~x;
+ for i in 0 to (6-is32b)
+ step = 1<<i
+ imm = (RB>>(i*8))&0xff
+ x = dorow(imm, x, step, is32b)
return x;
}
```
-# gorc
+| 0.5|6.10|11.15|16.20 |21..28 | 29.30|31| name | Form |
+| -- | -- | --- | --- | ----- | -----|--| ------ | ----- |
+| NN | RT | RA | s0-4 | im0-7 | 1 iv |s5| grevlogi | |
+| NN | RT | RA | RB | im0-7 | 01 |0 | grevlog | |
-based on RV bitmanip, gorc is superceded by grevlut
-
-```
-uint32_t gorc32(uint32_t RA, uint32_t RB)
-{
- uint32_t x = RA;
- int shamt = RB & 31;
- if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
- if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
- return x;
-}
-uint64_t gorc64(uint64_t RA, uint64_t RB)
-{
- uint64_t x = RA;
- int shamt = RB & 63;
- if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
- ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
- if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
- ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
- ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
- ((x & 0xFF00FF00FF00FF00LL) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
- ((x & 0xFFFF0000FFFF0000LL) >> 16);
- if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
- ((x & 0xFFFFFFFF00000000LL) >> 32);
- return x;
-}
-
-```
+An equivalent to `grevlogw` may be synthesised by setting the
+appropriate bits in RB to set the top half of RT to zero.
+Thus an explicit grevlogw instruction is not necessary.
# xperm
# bitmatrix
+bmatflip and bmatxor is found in the Cray XMT, and in x86 is known
+as GF2P8AFFINEQB. uses:
+
+* <https://gist.github.com/animetosho/d3ca95da2131b5813e16b5bb1b137ca0>
+* SM4, Reed Solomon, RAID6
+ <https://stackoverflow.com/questions/59124720/what-are-the-avx-512-galois-field-related-instructions-for>
+* Vector bit-reverse <https://reviews.llvm.org/D91515?id=305411>
+* Affine Inverse <https://github.com/HJLebbink/asm-dude/wiki/GF2P8AFFINEINVQB>
+
+| 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name | Form |
+| -- | -- | --- | --- | -- | ----- | -------- |--| ---- | ------- |
+| NN | RS | RA |im04 | im5| 1 1 | im67 00 110 |Rc| bmatxori | TODO |
+
+
```
uint64_t bmatflip(uint64_t RA)
{
x = shfl64(x, 31);
return x;
}
-uint64_t bmatxor(uint64_t RA, uint64_t RB)
-{
+
+uint64_t bmatxori(uint64_t RS, uint64_t RA, uint8_t imm) {
+ // transpose of RA
+ uint64_t RAt = bmatflip(RA);
+ uint8_t u[8]; // rows of RS
+ uint8_t v[8]; // cols of RA
+ for (int i = 0; i < 8; i++) {
+ u[i] = RS >> (i*8);
+ v[i] = RAt >> (i*8);
+ }
+ uint64_t bit, x = 0;
+ for (int i = 0; i < 64; i++) {
+ bit = (imm >> (i%8)) & 1;
+ bit ^= pcnt(u[i / 8] & v[i % 8]) & 1;
+ x |= bit << i;
+ }
+ return x;
+}
+
+uint64_t bmatxor(uint64_t RA, uint64_t RB) {
+ return bmatxori(RA, RB, 0xff)
+}
+
+uint64_t bmator(uint64_t RA, uint64_t RB) {
// transpose of RB
uint64_t RBt = bmatflip(RB);
uint8_t u[8]; // rows of RA
}
uint64_t x = 0;
for (int i = 0; i < 64; i++) {
- if (pcnt(u[i / 8] & v[i % 8]) & 1)
+ if ((u[i / 8] & v[i % 8]) != 0)
x |= 1LL << i;
}
return x;
}
-uint64_t bmator(uint64_t RA, uint64_t RB)
-{
+
+uint64_t bmatand(uint64_t RA, uint64_t RB) {
// transpose of RB
uint64_t RBt = bmatflip(RB);
uint8_t u[8]; // rows of RA
}
uint64_t x = 0;
for (int i = 0; i < 64; i++) {
- if ((u[i / 8] & v[i % 8]) != 0)
+ if ((u[i / 8] & v[i % 8]) == 0xff)
x |= 1LL << i;
}
return x;
}
-
```
# Introduction to Carry-less and GF arithmetic
(RS) = gfpmsubr(factor1, factor2, term)
```
-# Already in POWER ISA
+# Already in POWER ISA or subsumed
+
+Lists operations either included as part of
+other bitmanip operations, or are already in
+Power ISA.
+
+## cmix
+
+based on RV bitmanip, covered by ternlog bitops
+
+```
+uint_xlen_t cmix(uint_xlen_t RA, uint_xlen_t RB, uint_xlen_t RC) {
+ return (RA & RB) | (RC & ~RB);
+}
+```
## count leading/trailing zeros with mask
## bit to byte permute
similar to matrix permute in RV bitmanip, which has XOR and OR variants,
-these perform a transpose. TODO this looks VSX is there a scalar variant
+these perform a transpose (bmatflip).
+TODO this looks VSX is there a scalar variant
in v3.0/1 already
do j = 0 to 7
b = VSR[VRB+32].dword[i].byte[k].bit[j]
VSR[VRT+32].dword[i].byte[j].bit[k] = b
+## grev
+
+superceded by grevlut
+
+based on RV bitmanip, this is also known as a butterfly network. however
+where a butterfly network allows setting of every crossbar setting in
+every row and every column, generalised-reverse (grev) only allows
+a per-row decision: every entry in the same row must either switch or
+not-switch.
+
+<img src="https://upload.wikimedia.org/wikipedia/commons/thumb/8/8c/Butterfly_Network.jpg/474px-Butterfly_Network.jpg" />
+
+```
+uint64_t grev64(uint64_t RA, uint64_t RB)
+{
+ uint64_t x = RA;
+ int shamt = RB & 63;
+ if (shamt & 1) x = ((x & 0x5555555555555555LL) << 1) |
+ ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
+ if (shamt & 2) x = ((x & 0x3333333333333333LL) << 2) |
+ ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
+ if (shamt & 4) x = ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
+ ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
+ if (shamt & 8) x = ((x & 0x00FF00FF00FF00FFLL) << 8) |
+ ((x & 0xFF00FF00FF00FF00LL) >> 8);
+ if (shamt & 16) x = ((x & 0x0000FFFF0000FFFFLL) << 16) |
+ ((x & 0xFFFF0000FFFF0000LL) >> 16);
+ if (shamt & 32) x = ((x & 0x00000000FFFFFFFFLL) << 32) |
+ ((x & 0xFFFFFFFF00000000LL) >> 32);
+ return x;
+}
+
+```
+
+## gorc
+
+based on RV bitmanip, gorc is superceded by grevlut
+
+```
+uint32_t gorc32(uint32_t RA, uint32_t RB)
+{
+ uint32_t x = RA;
+ int shamt = RB & 31;
+ if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
+ if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+ return x;
+}
+uint64_t gorc64(uint64_t RA, uint64_t RB)
+{
+ uint64_t x = RA;
+ int shamt = RB & 63;
+ if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
+ ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
+ if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
+ ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
+ ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
+ ((x & 0xFF00FF00FF00FF00LL) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
+ ((x & 0xFFFF0000FFFF0000LL) >> 16);
+ if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
+ ((x & 0xFFFFFFFF00000000LL) >> 32);
+ return x;
+}
+
+```
+
+
# Appendix
see [[bitmanip/appendix]]
projects / libreriscv.git / blobdiff