* grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
* remove Rc=1 from ternlog due to conflicts in encoding as well
as saving space <https://bugs.libre-soc.org/show_bug.cgi?id=753#c5>
+* GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
# bitmanipulation
**DRAFT STATUS**
+pseudocode: <https://libre-soc.org/openpower/isa/bitmanip/>
+
this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
Vectorisation Context is provided by [[openpower/sv]].
ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
-general-purpose Galois Field operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
+general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
the [[sv/av_opcodes]] as well as [[sv/setvl]]
# summary
-minor opcode allocation
+two major opcodes are needed
+
+ternlog has its own major opcode
+
+| 29.30 |31| name |
+| ------ |--| --------- |
+| 0 0 |Rc| ternlogi |
+| 0 1 |sz| ternlogv |
+| 1 iv | | grevlogi |
+
+2nd major opcode for other bitmanip: minor opcode allocation
+
+| 28.30 |31| name |
+| ------ |--| --------- |
+| -00 |0 | xpermi |
+| -00 |1 | grevlog |
+| -01 | | crternlog |
+| 010 |Rc| bitmask |
+| 011 | | gf/cl madd* |
+| 110 |Rc| 1/2-op |
+| 111 | | bmrevi |
- | 28.30 |31| name |
- | ------ |--| --------- |
- | 00 |0 | ternlogi |
- | 000 |1 | ternlog |
- | 100 |1 | reserved |
- | 010 |Rc| bitmask |
- | 011 |Rc| gf* |
- | 101 |1 | ternlogv |
- | 101 |0 | ternlogcr |
- | 110 |Rc| 1/2-op |
- | 111 |Rc| 3-op |
1-op and variants
| RT | RA | RB | type | minmax |
| RT | RA | RB | | av abs avgadd |
| RT | RA | RB | type | vmask ops |
-| RT | RA | RB | | |
+| RT | RA | RB | | |
3 ops
-* bitmask set/extract
-* ternlog bitops
-* GF
+* grevlog
+* GF mul-add
+* bitmask-reverse
TODO: convert all instructions to use RT and not RS
-| 0.5|6.10|11.15|16.20|21..25 | 26....30 |31| name |
-| -- | -- | --- | --- | ----- | -------- |--| ------ |
-| NN | RT | RA | RB | RC | mode 000 |1 | ternlog |
-| NN | RT | RA | RB | im0-4 | im5-7 00 |0 | ternlogi |
-| NN | RS | RA | RB | RC | 00 011 |Rc| gfmul |
-| NN | RS | RA | RB | RC | 01 011 |Rc| gfadd |
-| NN | RT | RA | RB | deg | 10 011 |Rc| gfinv |
-| NN | RS | RA | RB | deg | 11 011 |Rc| gfmuli |
-| NN | RS | RA | RB | deg | 11 111 |Rc| gfaddi |
-
-| 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31| name |
-| -- | -- | --- | ----- | ---- | ----- |--| ------ |
-| NN | RT | RA | imm | mask | 101 |1 | ternlogv |
-
-| 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31| name |
-| -- | -- | --- | --- |- |-----|----- | -----|--| -------|
-| NN | BA | BB | BC |0 |imm | mask | 101 |0 | ternlogcr |
+| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|name|
+| -- | -- | --- | --- | --- |-----|----- | -----|--|----|
+| NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|crternlog|
+
+| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
+| -- | -- | --- | --- | ----- | -------- |--| ------ |
+| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi |
+| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
+| NN | | | | | ..... 01 |0 | crternlog |
+| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask* |
+| NN | RS | RA | RB | RC | 00 011 |0 | gfbmadd |
+| NN | RS | RA | RB | RC | 00 011 |1 | gfbmaddsub |
+| NN | RS | RA | RB | RC | 01 011 |0 | clmadd |
+| NN | RS | RA | RB | RC | 01 011 |1 | clmaddsub |
+| NN | RS | RA | RB | RC | 10 011 |0 | gfpmadd |
+| NN | RS | RA | RB | RC | 10 011 |1 | gfpmaddsub |
+| NN | RS | RA | RB | RC | 11 011 | | rsvd |
+| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi |
ops (note that av avg and abs as well as vec scalar mask
are included here)
| 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
| -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
-| NN | RA | RB | | 0 | | 0000 110 |Rc| rsvd |
-| NN | RA | RB | RC | 1 | itype | 0000 110 |Rc| xperm |
-| NN | RA | RB | RC | 0 | itype | 0100 110 |Rc| minmax |
-| NN | RA | RB | RC | 1 | 00 | 0100 110 |Rc| av avgadd |
-| NN | RA | RB | RC | 1 | 01 | 0100 110 |Rc| av abs |
-| NN | RA | RB | | 1 | 10 | 0100 110 |Rc| rsvd |
-| NN | RA | RB | | 1 | 11 | 0100 110 |Rc| rsvd |
-| NN | RA | RB | sh | SH | itype | 1000 110 |Rc| bmopsi |
-| NN | RA | RB | | | | 1100 110 |Rc| rsvd |
-| NN | RA | RB | | 1 | | 0001 110 |Rc| rsvd |
+| NN | RS | me | sh | SH | ME 0 | nn00 110 |Rc| bmopsi |
+| NN | RS | RB | sh | SH | / 0 | nn00 110 |Rc| bmopsi |
+| NN | RT | RA | RB | | | 1100 110 |Rc| srsvd |
+| NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
+| NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
+| NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| |
+| NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv |
| NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm |
| NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm |
| NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm |
| NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop |
-| NN | RA | RB | | 0 | | 0101 110 |Rc| rsvd |
+| NN | RT | RA | RB | 1 | itype | 0101 110 |Rc| xperm |
+| NN | RA | RB | RC | 0 | itype | 0101 110 |Rc| minmax |
+| NN | RA | RB | RC | 1 | 00 | 0101 110 |Rc| av avgadd |
+| NN | RA | RB | RC | 1 | 01 | 0101 110 |Rc| av abs |
+| NN | RA | RB | | 1 | 10 | 0101 110 |Rc| rsvd |
+| NN | RA | RB | | 1 | 11 | 0101 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc |
| NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci |
| NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw |
| NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw |
| NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi |
| NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor |
-| NN | RA | RB | RC | 0 | 10 | 0010 110 |Rc| shfl |
-| NN | RA | RB | sh | SH | 10 | 1010 110 |Rc| shfli |
-| NN | RA | RB | RC | 0 | 10 | 0110 110 |Rc| shflw |
-| NN | RA | RB | RC | | 10 | 1110 110 |Rc| rsvd |
+| NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr |
| NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh |
| NN | | | | | | --11 110 |Rc| setvl |
-# bit to byte permute
+# ternlog bitops
+
+Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
-similar to matrix permute in RV bitmanip, which has XOR and OR variants
+Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
+
+## ternlogi
+
+| 0.5|6.10|11.15|16.20| 21..28|29.30|31|
+| -- | -- | --- | --- | ----- | --- |--|
+| NN | RT | RA | RB | im0-7 | 00 |Rc|
+
+ lut3(imm, a, b, c):
+ idx = c << 2 | b << 1 | a
+ return imm[idx] # idx by LSB0 order
+
+ for i in range(64):
+ RT[i] = lut3(imm, RB[i], RA[i], RT[i])
+
+## ternlogv
+
+also, another possible variant involving swizzle-like selection
+and masking, this only requires 3 64 bit registers (RA, RS, RB) and
+only 16 LUT3s.
+
+Note however that unless XLEN matches sz, this instruction
+is a Read-Modify-Write: RS must be read as a second operand
+and all unmodified bits preserved. SVP64 may provide limited
+alternative destination for RS from RS-as-source, but again
+all unmodified bits must still be copied.
+
+| 0.5|6.10|11.15|16.20|21.28 | 29.30 |31|
+| -- | -- | --- | --- | ---- | ----- |--|
+| NN | RS | RA | RB |idx0-3| 01 |sz|
+
+ SZ = (1+sz) * 8 # 8 or 16
+ raoff = MIN(XLEN, idx0 * SZ)
+ rboff = MIN(XLEN, idx1 * SZ)
+ rcoff = MIN(XLEN, idx2 * SZ)
+ rsoff = MIN(XLEN, idx3 * SZ)
+ imm = RB[0:8]
+ for i in range(MIN(XLEN, SZ)):
+ ra = RA[raoff:+i]
+ rb = RA[rboff+i]
+ rc = RA[rcoff+i]
+ res = lut3(imm, ra, rb, rc)
+ RS[rsoff+i] = res
+
+## ternlogcr
+
+another mode selection would be CRs not Ints.
+
+| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
+| -- | -- | --- | --- | --- |-----|----- | -----|--|
+| NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|
+
+ mask = m0-3,m4
+ for i in range(4):
+ if not mask[i] continue
+ crregs[BT][i] = lut3(imm,
+ crregs[BA][i],
+ crregs[BB][i],
+ crregs[BC][i])
- do j = 0 to 7
- do k = 0 to 7
- b = VSR[VRB+32].dword[i].byte[k].bit[j]
- VSR[VRT+32].dword[i].byte[j].bit[k] = b
# int min/max
```
-# ternlog bitops
-
-Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit immediate, or in another register.
-
-Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
-
-## ternlogi
-
-| 0.5|6.10|11.15|16.20| 21..25| 26..30 |31|
-| -- | -- | --- | --- | ----- | -------- |--|
-| NN | RT | RA | RB | im0-4 | im5-7 00 |0 |
-
- for i in range(64):
- idx = RT[i] << 2 | RA[i] << 1 | RB[i]
- RT[i] = (imm & (1<<idx)) != 0
-
-bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
-
-## ternlog
-
-a 4 operand variant which becomes more along the lines of an FPGA:
-
-| 0.5|6.10|11.15|16.20|21.25| 26...30 |31|
-| -- | -- | --- | --- | --- | -------- |--|
-| NN | RT | RA | RB | RC | mode 100 |1 |
-
- for i in range(64):
- idx = RT[i] << 2 | RA[i] << 1 | RB[i]
- RT[i] = (RC & (1<<idx)) != 0
-
-mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
-3 modes.
-
-## ternlogv
-
-also, another possible variant involving swizzle and vec4:
-
-| 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
-| -- | -- | --- | ----- | ---- | ----- |--|
-| NN | RT | RA | imm | mask | 101 |1 |
-
- for i in range(8):
- idx = RA.x[i] << 2 | RA.y[i] << 1 | RA.z[i]
- res = (imm & (1<<idx)) != 0
- for j in range(3):
- if mask[j]: RT[i+j*8] = res
-
-## ternlogcr
-
-another mode selection would be CRs not Ints.
-
-| 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|
-| -- | -- | --- | --- |- |-----|----- | -----|--|
-| NN | BA | BB | BC |0 |imm | mask | 101 |0 |
-
- for i in range(4):
- if not mask[i] continue
- idx = crregs[BA][i] << 2 |
- crregs[BB][i] << 1 |
- crregs[BC][i]
- crregs[BA][i] = (imm & (1<<idx)) != 0
-
## cmix
based on RV bitmanip, covered by ternlog bitops
| 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
| -- | -- | --- | --- | --- | ------- |--| ----- |
-| NN | RT | RA | RB | RC | mode 010 |Rc| bm* |
-| NN | RT | RA | RB | RC | 0 1 111 |Rc| bmrev |
+| NN | RS | RA | RB | RC | mode 010 |Rc| bm* |
+Immediate-variant is an overwrite form:
+
+| 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
+| -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
+| NN | RS | RB | sh | SH | itype | 1000 110 |Rc| bm*i |
```
-uint_xlen_t bmset(RA, RB, sh)
+def MASK(x, y):
+ if x < y:
+ x = x+1
+ mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
+ mask_b = ((1 << y) - 1) & ((1 << 64) - 1)
+ elif x == y:
+ return 1 << x
+ else:
+ x = x+1
+ mask_a = ((1 << x) - 1) & ((1 << 64) - 1)
+ mask_b = (~((1 << y) - 1)) & ((1 << 64) - 1)
+ return mask_a ^ mask_b
+
+
+uint_xlen_t bmset(RS, RB, sh)
{
int shamt = RB & (XLEN - 1);
- mask = (2<<sh)-1;
- return RA | (mask << shamt);
+ return RS | MASK(shamt, sh)
}
-uint_xlen_t bmclr(RA, RB, sh)
+uint_xlen_t bmclr(RS, RB, sh)
{
int shamt = RB & (XLEN - 1);
- mask = (2<<sh)-1;
- return RA & ~(mask << shamt);
+ return RS & ~MASK(shamt, sh)
}
-uint_xlen_t bminv(RA, RB, sh)
+uint_xlen_t bminv(RS, RB, sh)
{
int shamt = RB & (XLEN - 1);
- mask = (2<<sh)-1;
- return RA ^ (mask << shamt);
+ return RS ^ MASK(shamt, sh)
}
-uint_xlen_t bmext(RA, RB, sh)
+uint_xlen_t bmext(RS, RB, sh)
{
int shamt = RB & (XLEN - 1);
mask = (2<<sh)-1;
- return mask & (RA >> shamt);
+ return mask & (RS >> shamt);
}
```
-bitmask extract with reverse. can be done by bitinverting all of RA and getting bits of RA from the opposite end.
+bitmask extract with reverse. can be done by bit-order-inverting all of RB and getting bits of RB from the opposite end.
+
+when RA is zero, no shift occurs. this makes bmextrev useful for
+simply reversing all bits of a register.
```
-msb = rb[5:0];
-rev[0:msb] = ra[msb:0];
+msb = ra[5:0];
+rev[0:msb] = rb[msb:0];
rt = ZE(rev[msb:0]);
uint_xlen_t bmextrev(RA, RB, sh)
{
- int shamt = (RB & (XLEN - 1));
+ int shamt = XLEN-1;
+ if (RA != 0) shamt = (GPR(RA) & (XLEN - 1));
shamt = (XLEN-1)-shamt; # shift other end
- bra = bitreverse(RA) # swap LSB-MSB
+ bra = bitreverse(RB) # swap LSB-MSB
mask = (2<<sh)-1;
return mask & (bra >> shamt);
}
| 0.5|6.10|11.15|16.20|21.26| 27..30 |31| name |
| -- | -- | --- | --- | --- | ------- |--| ------ |
-| NN | RT | RA | RB | sh | 0 111 |Rc| bmrevi |
+| NN | RT | RA | RB | sh | 1 011 |Rc| bmrevi |
+
+
+# grevlut
+
+generalised reverse combined with a pair of LUT2s and allowing
+a constant `0b0101...0101` when RA=0, and an option to invert
+(including when RA=0, giving a constant 0b1010...1010 as the
+initial value) provides a wide range of instructions
+and a means to set regular 64 bit patterns in one
+32 bit instruction.
+
+the two LUT2s are applied left-half (when not swapping)
+and right-half (when swapping) so as to allow a wider
+range of options.
+
+<img src="/openpower/sv/grevlut2x2.jpg" width=700 />
+
+* A value of `0b11001010` for the immediate provides
+the functionality of a standard "grev".
+* `0b11101110` provides gorc
+
+grevlut should be arranged so as to produce the constants
+needed to put into bext (bitextract) so as in turn to
+be able to emulate x86 pmovmask instructions <https://www.felixcloutier.com/x86/pmovmskb>.
+This only requires 2 instructions (grevlut, bext).
+
+Note that if the mask is required to be placed
+directly into CR Fields (for use as CR Predicate
+masks rather than a integer mask) then sv.ori
+may be used instead, bearing in mind that sv.ori
+is a 64-bit instruction, and `VL` must have been
+set to the required length:
+
+ sv.ori./elwid=8 r10.v, r10.v, 0
+
+The following settings provide the required mask constants:
+
+| RA | RB | imm | iv | result |
+| ------- | ------- | ---------- | -- | ---------- |
+| 0x555.. | 0b10 | 0b01101100 | 0 | 0x111111... |
+| 0x555.. | 0b110 | 0b01101100 | 0 | 0x010101... |
+| 0x555.. | 0b1110 | 0b01101100 | 0 | 0x00010001... |
+| 0x555.. | 0b10 | 0b11000110 | 1 | 0x88888... |
+| 0x555.. | 0b110 | 0b11000110 | 1 | 0x808080... |
+| 0x555.. | 0b1110 | 0b11000110 | 1 | 0x80008000... |
+Better diagram showing the correct ordering of shamt (RB). A LUT2
+is applied to all locations marked in red using the first 4
+bits of the immediate, and a separate LUT2 applied to all
+locations in green using the upper 4 bits of the immediate.
+
+<img src="/openpower/sv/grevlut.png" width=700 />
+
+demo code [[openpower/sv/grevlut.py]]
+
+```
+lut2(imm, a, b):
+ idx = b << 1 | a
+ return imm[idx] # idx by LSB0 order
+
+dorow(imm8, step_i, chunksize):
+ for j in 0 to 63:
+ if (j&chunk_size) == 0
+ imm = imm8[0..3]
+ else
+ imm = imm8[4..7]
+ step_o[j] = lut2(imm, step_i[j], step_i[j ^ chunk_size])
+ return step_o
+
+uint64_t grevlut64(uint64_t RA, uint64_t RB, uint8 imm, bool iv)
+{
+ uint64_t x = 0x5555_5555_5555_5555;
+ if (RA != 0) x = GPR(RA);
+ if (iv) x = ~x;
+ int shamt = RB & 63;
+ for i in 0 to 6
+ step = 1<<i
+ if (shamt & step) x = dorow(imm, x, step)
+ return x;
+}
+
+```
+
+| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
+| -- | -- | --- | --- | ----- | -------- |--| ------ |
+| NN | RT | RA | s0-4 | im0-4 | im5-7 1 iv |s5| grevlogi |
+| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
# grev
```
-# shuffle / unshuffle
+# xperm
-based on RV bitmanip
+based on RV bitmanip.
-```
-uint32_t shfl32(uint32_t RA, uint32_t RB)
-{
- uint32_t x = RA;
- int shamt = RB & 15;
- if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
- if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
- if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
- if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
- return x;
-}
-uint32_t unshfl32(uint32_t RA, uint32_t RB)
-{
- uint32_t x = RA;
- int shamt = RB & 15;
- if (shamt & 1) x = shuffle32_stage(x, 0x44444444, 0x22222222, 1);
- if (shamt & 2) x = shuffle32_stage(x, 0x30303030, 0x0c0c0c0c, 2);
- if (shamt & 4) x = shuffle32_stage(x, 0x0f000f00, 0x00f000f0, 4);
- if (shamt & 8) x = shuffle32_stage(x, 0x00ff0000, 0x0000ff00, 8);
- return x;
-}
+RA contains a vector of indices to select parts of RB to be
+copied to RT. The immediate-variant allows up to an 8 bit
+pattern (repeated) to be targetted at different parts of RT
-uint64_t shuffle64_stage(uint64_t src, uint64_t maskL, uint64_t maskR, int N)
-{
- uint64_t x = src & ~(maskL | maskR);
- x |= ((src << N) & maskL) | ((src >> N) & maskR);
- return x;
-}
-uint64_t shfl64(uint64_t RA, uint64_t RB)
-{
- uint64_t x = RA;
- int shamt = RB & 31;
- if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
- 0x00000000ffff0000LL, 16);
- if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
- 0x0000ff000000ff00LL, 8);
- if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
- 0x00f000f000f000f0LL, 4);
- if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
- 0x0c0c0c0c0c0c0c0cLL, 2);
- if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
- 0x2222222222222222LL, 1);
- return x;
-}
-uint64_t unshfl64(uint64_t RA, uint64_t RB)
+```
+uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
{
- uint64_t x = RA;
- int shamt = RB & 31;
- if (shamt & 1) x = shuffle64_stage(x, 0x4444444444444444LL,
- 0x2222222222222222LL, 1);
- if (shamt & 2) x = shuffle64_stage(x, 0x3030303030303030LL,
- 0x0c0c0c0c0c0c0c0cLL, 2);
- if (shamt & 4) x = shuffle64_stage(x, 0x0f000f000f000f00LL,
- 0x00f000f000f000f0LL, 4);
- if (shamt & 8) x = shuffle64_stage(x, 0x00ff000000ff0000LL,
- 0x0000ff000000ff00LL, 8);
- if (shamt & 16) x = shuffle64_stage(x, 0x0000ffff00000000LL,
- 0x00000000ffff0000LL, 16);
- return x;
+ uint_xlen_t r = 0;
+ uint_xlen_t sz = 1LL << sz_log2;
+ uint_xlen_t mask = (1LL << sz) - 1;
+ uint_xlen_t RA = imm8 | imm8<<8 | ... | imm8<<56;
+ for (int i = 0; i < XLEN; i += sz) {
+ uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
+ if (pos < XLEN)
+ r |= ((RB >> pos) & mask) << i;
+ }
+ return r;
}
-```
-
-# xperm
-
-based on RV bitmanip
-
-```
uint_xlen_t xperm(uint_xlen_t RA, uint_xlen_t RB, int sz_log2)
{
uint_xlen_t r = 0;
uint_xlen_t sz = 1LL << sz_log2;
uint_xlen_t mask = (1LL << sz) - 1;
for (int i = 0; i < XLEN; i += sz) {
- uint_xlen_t pos = ((RB >> i) & mask) << sz_log2;
+ uint_xlen_t pos = ((RA >> i) & mask) << sz_log2;
if (pos < XLEN)
- r |= ((RA >> pos) & mask) << i;
+ r |= ((RB >> pos) & mask) << i;
}
return r;
}
```
-# Galois Field
+# Instructions for Carry-less Operations aka. Polynomials with coefficients in `GF(2)`
-see <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
+Carry-less addition/subtraction is simply XOR, so a `cladd`
+instruction is not provided since the `xor[i]` instruction can be used instead.
-## Multiply
+These are operations on polynomials with coefficients in `GF(2)`, with the
+polynomial's coefficients packed into integers with the following algorithm:
+
+[[!inline pagenames="openpower/sv/bitmanip/pack_poly.py" raw="true" feeds="no" actions="yes"]]
+
+## Carry-less Multiply Instructions
+
+based on RV bitmanip
+see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
+<https://www.felixcloutier.com/x86/pclmulqdq> and
+<https://en.m.wikipedia.org/wiki/Carry-less_product>
+
+They are worth adding as their own non-overwrite operations
+(in the same pipeline).
+
+### `clmul` Carry-less Multiply
+
+[[!inline pagenames="openpower/sv/bitmanip/clmul.py" raw="true" feeds="no" actions="yes"]]
+
+### `clmulh` Carry-less Multiply High
+
+[[!inline pagenames="openpower/sv/bitmanip/clmulh.py" raw="true" feeds="no" actions="yes"]]
+
+### `clmulr` Carry-less Multiply (Reversed)
+
+Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
+bit-reversed inputs.
+
+[[!inline pagenames="openpower/sv/bitmanip/clmulr.py" raw="true" feeds="no" actions="yes"]]
+
+## `clmadd` Carry-less Multiply-Add
+
+```
+clmadd RT, RA, RB, RC
+```
+
+```
+(RT) = clmul((RA), (RB)) ^ (RC)
+```
+
+## `cltmadd` Twin Carry-less Multiply-Add (for FFTs)
+
+```
+cltmadd RT, RA, RB, RC
+```
+
+TODO: add link to explanation for where `RS` comes from.
+
+```
+temp = clmul((RA), (RB)) ^ (RC)
+(RT) = temp
+(RS) = temp
+```
+
+## `cldivrem` Carry-less Division and Remainder
+
+`cldivrem` isn't an actual instruction, but is just used in the pseudo-code
+for other instructions.
-this requires 3 parameters and a "degree"
+[[!inline pagenames="openpower/sv/bitmanip/cldivrem.py" raw="true" feeds="no" actions="yes"]]
- RT = GFMUL(RA, RB, gfdegree, modulo=RC)
+## `cldiv` Carry-less Division
-realistically with the degree also needing to be an immediate it should be brought down to an overwrite version:
+```
+cldiv RT, RA, RB
+```
+
+```
+n = (RA)
+d = (RB)
+q, r = cldivrem(n, d, width=XLEN)
+(RT) = q
+```
+
+## `clrem` Carry-less Remainder
+
+```
+clrem RT, RA, RB
+```
+
+```
+n = (RA)
+d = (RB)
+q, r = cldivrem(n, d, width=XLEN)
+(RT) = r
+```
+
+# Instructions for Binary Galois Fields `GF(2^m)`
+
+see:
+
+* <https://courses.csail.mit.edu/6.857/2016/files/ffield.py>
+* <https://engineering.purdue.edu/kak/compsec/NewLectures/Lecture7.pdf>
+* <https://foss.heptapod.net/math/libgf2/-/blob/branch/default/src/libgf2/gf2.py>
+
+Binary Galois Field addition/subtraction is simply XOR, so a `gfbadd`
+instruction is not provided since the `xor[i]` instruction can be used instead.
+
+## `GFBREDPOLY` SPR -- Reducing Polynomial
+
+In order to save registers and to make operations orthogonal with standard
+arithmetic, the reducing polynomial is stored in a dedicated SPR `GFBREDPOLY`.
+This also allows hardware to pre-compute useful parameters (such as the
+degree, or look-up tables) based on the reducing polynomial, and store them
+alongside the SPR in hidden registers, only recomputing them whenever the SPR
+is written to, rather than having to recompute those values for every
+instruction.
+
+Because Galois Fields require the reducing polynomial to be an irreducible
+polynomial, that guarantees that any polynomial of `degree > 1` must have
+the LSB set, since otherwise it would be divisible by the polynomial `x`,
+making it reducible, making whatever we're working on no longer a Field.
+Therefore, we can reuse the LSB to indicate `degree == XLEN`.
+
+```python
+def decode_reducing_polynomial(GFBREDPOLY, XLEN):
+ """returns the decoded coefficient list in LSB to MSB order,
+ len(retval) == degree + 1"""
+ v = GFBREDPOLY & ((1 << XLEN) - 1) # mask to XLEN bits
+ if v == 0 or v == 2: # GF(2)
+ return [0, 1] # degree = 1, poly = x
+ if v & 1:
+ degree = floor_log2(v)
+ else:
+ # all reducing polynomials of degree > 1 must have the LSB set,
+ # because they must be irreducible polynomials (meaning they
+ # can't be factored), if the LSB was clear, then they would
+ # have `x` as a factor. Therefore, we can reuse the LSB clear
+ # to instead mean the polynomial has degree XLEN.
+ degree = XLEN
+ v |= 1 << XLEN
+ v |= 1 # LSB must be set
+ return [(v >> i) & 1 for i in range(1 + degree)]
+```
+
+## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
+
+unless this is an immediate op, `mtspr` is completely sufficient.
+
+## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
+
+```
+gfbmul RT, RA, RB
+```
+
+```
+(RT) = gfbmul((RA), (RB))
+```
+
+## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
+
+```
+gfbmadd RT, RA, RB, RC
+```
+
+```
+(RT) = gfbadd(gfbmul((RA), (RB)), (RC))
+```
+
+## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
+
+```
+gfbtmadd RT, RA, RB, RC
+```
+
+TODO: add link to explanation for where `RS` comes from.
+
+```
+temp = gfbadd(gfbmul((RA), (RB)), (RC))
+(RT) = temp
+(RS) = temp
+```
+
+## `gfbinv` -- Binary Galois Field `GF(2^m)` Inverse
+
+```
+gfbinv RT, RA
+```
+
+```
+(RT) = gfbinv((RA))
+```
+
+# Instructions for Prime Galois Fields `GF(p)`
+
+## Helper algorithms
+
+```python
+def int_to_gfp(int_value, prime):
+ return int_value % prime # follows Python remainder semantics
+```
+
+## `GFPRIME` SPR -- Prime Modulus For `gfp*` Instructions
+
+## `gfpadd` Prime Galois Field `GF(p)` Addition
+
+```
+gfpadd RT, RA, RB
+```
+
+```
+(RT) = int_to_gfp((RA) + (RB), GFPRIME)
+```
+
+the addition happens on infinite-precision integers
+
+## `gfpsub` Prime Galois Field `GF(p)` Subtraction
+
+```
+gfpsub RT, RA, RB
+```
+
+```
+(RT) = int_to_gfp((RA) - (RB), GFPRIME)
+```
+
+the subtraction happens on infinite-precision integers
+
+## `gfpmul` Prime Galois Field `GF(p)` Multiplication
+
+```
+gfpmul RT, RA, RB
+```
+
+```
+(RT) = int_to_gfp((RA) * (RB), GFPRIME)
+```
+
+the multiplication happens on infinite-precision integers
+
+## `gfpinv` Prime Galois Field `GF(p)` Invert
+
+```
+gfpinv RT, RA
+```
+
+Some potential hardware implementations are found in:
+<https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
- RS = GFMUL(RS, RA, gfdegree, modulo=RC)
- RS = GFMUL(RS, RA, gfdegree=RB, modulo=RC)
+```
+(RT) = gfpinv((RA), GFPRIME)
+```
+
+the multiplication happens on infinite-precision integers
+
+## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
+
+```
+gfpmadd RT, RA, RB, RC
+```
+
+```
+(RT) = int_to_gfp((RA) * (RB) + (RC), GFPRIME)
+```
+
+the multiplication and addition happens on infinite-precision integers
+
+## `gfpmsub` Prime Galois Field `GF(p)` Multiply-Subtract
+
+```
+gfpmsub RT, RA, RB, RC
+```
+
+```
+(RT) = int_to_gfp((RA) * (RB) - (RC), GFPRIME)
+```
+
+the multiplication and subtraction happens on infinite-precision integers
+
+## `gfpmsubr` Prime Galois Field `GF(p)` Multiply-Subtract-Reversed
-| 0.5|6.10|11.15|16.20|21.25| 26..30 |31|
-| -- | -- | --- | --- | --- | ------- |--|
-| NN | RS | RA | deg | RC | 00 011 |Rc|
-| NN | RS | RA | RB | RC | 11 011 |Rc|
+```
+gfpmsubr RT, RA, RB, RC
+```
+
+```
+(RT) = int_to_gfp((RC) - (RA) * (RB), GFPRIME)
+```
-where the SimpleV variant may override RS-as-src differently from RS-as-dest
+the multiplication and subtraction happens on infinite-precision integers
+
+## `gfpmaddsubr` Prime Galois Field `GF(p)` Multiply-Add and Multiply-Sub-Reversed (for FFT)
+
+```
+gfpmaddsubr RT, RA, RB, RC
+```
+
+TODO: add link to explanation for where `RS` comes from.
+
+```
+product = (RA) * (RB)
+term = (RC)
+(RT) = int_to_gfp(product + term, GFPRIME)
+(RS) = int_to_gfp(term - product, GFPRIME)
+```
+
+the multiplication, addition, and subtraction happens on infinite-precision integers
+
+## Twin Butterfly (Tukey-Cooley) Mul-add-sub
+
+used in combination with SV FFT REMAP to perform
+a full NTT in-place. possible by having 3-in 2-out,
+to avoid the need for a temp register. RS is written
+to as well as RT.
+
+ gffmadd RT,RA,RC,RB (Rc=0)
+ gffmadd. RT,RA,RC,RB (Rc=1)
+
+Pseudo-code:
+
+ RT <- GFADD(GFMUL(RA, RC), RB))
+ RS <- GFADD(GFMUL(RA, RC), RB))
+
+
+## Multiply
+
+with the modulo and degree being in an SPR, multiply can be identical
+equivalent to standard integer add
+
+ RS = GFMUL(RA, RB)
+
+| 0.5|6.10|11.15|16.20|21.25| 26..30 |31|
+| -- | -- | --- | --- | --- | ------ |--|
+| NN | RT | RA | RB |11000| 01110 |Rc|
```
from functools import reduce
+def gf_degree(a) :
+ res = 0
+ a >>= 1
+ while (a != 0) :
+ a >>= 1;
+ res += 1;
+ return res
+
# constants used in the multGF2 function
mask1 = mask2 = polyred = None
-def setGF2(degree, irPoly):
+def setGF2(irPoly):
"""Define parameters of binary finite field GF(2^m)/g(x)
- - degree: extension degree of binary field
- irPoly: coefficients of irreducible polynomial g(x)
"""
+ # degree: extension degree of binary field
+ degree = gf_degree(irPoly)
+
def i2P(sInt):
"""Convert an integer into a polynomial"""
return [(sInt >> i) & 1
"""Multiply two polynomials in GF(2^m)/g(x)"""
p = 0
while p2:
+ # standard long-multiplication: check LSB and add
if p2 & 1:
p ^= p1
p1 <<= 1
+ # standard modulo: check MSB and add polynomial
if p1 & mask1:
p1 ^= polyred
p2 >>= 1
if __name__ == "__main__":
# Define binary field GF(2^3)/x^3 + x + 1
- setGF2(3, 0b1011)
+ setGF2(0b1011) # degree 3
# Evaluate the product (x^2 + x + 1)(x^2 + 1)
print("{:02x}".format(multGF2(0b111, 0b101)))
# Define binary field GF(2^8)/x^8 + x^4 + x^3 + x + 1
# (used in the Advanced Encryption Standard-AES)
- setGF2(8, 0b100011011)
+ setGF2(0b100011011) # degree 8
# Evaluate the product (x^7)(x^7 + x + 1)
print("{:02x}".format(multGF2(0b10000000, 0b10000011)))
```
-## GF add
- RS = GFADDI(RS, RA|0, gfdegree, modulo=RC)
- RS = GFADD(RS, RA|0, gfdegree=RB, modulo=RC)
+## GF(2^M) Inverse
-| 0.5|6.10|11.15|16.20|21.25| 26..30 |31| name |
-| -- | -- | --- | --- | --- | ------- |--| ----- |
-| NN | RS | RA | deg | RC | 0 1 011 |Rc| gfaddi |
-| NN | RS | RA | RB | RC | 1 1 111 |Rc| gfadd |
+```
+# https://bugs.libre-soc.org/show_bug.cgi?id=782#c33
+# https://ftp.libre-soc.org/ARITH18_Kobayashi.pdf
+def gf_invert(a) :
+
+ s = getGF2() # get the full polynomial (including the MSB)
+ r = a
+ v = 0
+ u = 1
+ j = 0
+
+ for i in range(1, 2*degree+1):
+ # could use count-trailing-1s here to skip ahead
+ if r & mask1: # test MSB of r
+ if s & mask1: # test MSB of s
+ s ^= r
+ v ^= u
+ s <<= 1 # shift left 1
+ if j == 0:
+ r, s = s, r # swap r,s
+ u, v = v<<1, u # shift v and swap
+ j = 1
+ else:
+ u >>= 1 # right shift left
+ j -= 1
+ else:
+ r <<= 1 # shift left 1
+ u <<= 1 # shift left 1
+ j += 1
+
+ return u
+```
-GFMOD is a pseudo-op where RA=0
+# GF2 (Carryless)
-## gf invert
+## GF2 (carryless) div and mod
```
def gf_degree(a) :
res += 1;
return res
-def gf_invert(a, mod=0x1B) :
- v = mod
- g1 = 1
- g2 = 0
- j = gf_degree(a) - 8
-
- while (a != 1) :
- if (j < 0) :
- a, v = v, a
- g1, g2 = g2, g1
- j = -j
-
- a ^= v << j
- g1 ^= g2 << j
-
- a %= 256 # Emulating 8-bit overflow
- g1 %= 256 # Emulating 8-bit overflow
-
- j = gf_degree(a) - gf_degree(v)
-
- return g1
+def FullDivision(self, f, v):
+ """
+ Takes two arguments, f, v
+ fDegree and vDegree are the degrees of the field elements
+ f and v represented as a polynomials.
+ This method returns the field elements a and b such that
+
+ f(x) = a(x) * v(x) + b(x).
+
+ That is, a is the divisor and b is the remainder, or in
+ other words a is like floor(f/v) and b is like f modulo v.
+ """
+
+ fDegree, vDegree = gf_degree(f), gf_degree(v)
+ res, rem = 0, f
+ for i in reversed(range(vDegree, fDegree+1):
+ if ((rem >> i) & 1): # check bit
+ res ^= (1 << (i - vDegree))
+ rem ^= ( v << (i - vDegree)))
+ return (res, rem)
```
-## carryless mul
+| 0.5|6.10|11.15|16.20| 21 | 22.23 | 24....30 |31| name |
+| -- | -- | --- | --- | -- | ----- | -------- |--| ---- |
+| NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
+| NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
+
+## GF2 carryless mul
based on RV bitmanip
-see https://en.wikipedia.org/wiki/CLMUL_instruction_set
+see <https://en.wikipedia.org/wiki/CLMUL_instruction_set> and
+<https://www.felixcloutier.com/x86/pclmulqdq> and
+<https://en.m.wikipedia.org/wiki/Carry-less_product>
these are GF2 operations with the modulo set to 2^degree.
they are worth adding as their own non-overwrite operations
return x;
}
```
+## carryless Twin Butterfly (Tukey-Cooley) Mul-add-sub
+
+used in combination with SV FFT REMAP to perform
+a full NTT in-place. possible by having 3-in 2-out,
+to avoid the need for a temp register. RS is written
+to as well as RT.
+
+ clfmadd RT,RA,RC,RB (Rc=0)
+ clfmadd. RT,RA,RC,RB (Rc=1)
+
+Pseudo-code:
+
+ RT <- CLMUL(RA, RC) ^ RB
+ RS <- CLMUL(RA, RC) ^ RB
+
# bitmatrix
RA = result
```
+# bit to byte permute
+
+similar to matrix permute in RV bitmanip, which has XOR and OR variants,
+these perform a transpose.
+
+ do j = 0 to 7
+ do k = 0 to 7
+ b = VSR[VRB+32].dword[i].byte[k].bit[j]
+ VSR[VRT+32].dword[i].byte[j].bit[k] = b
+
projects / libreriscv.git / blobdiff