pseudocode: [[openpower/isa/bitmanip]]
-this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
+this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
+Also included are DSP/Multimedia operations suitable for
+Audio/Video. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
Vectorisation Context is provided by [[openpower/sv]].
-When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
+When combined with SV, scalar variants of bitmanip operations found in VSX are added so that the Packed SIMD aspects of VSX may be retired as "legacy"
+in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
-the [[sv/av_opcodes]] as well as [[sv/setvl]]
+the [[sv/av_opcodes]] as well as [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
Useful resource:
TODO: convert all instructions to use RT and not RS
-| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|name|
-| -- | -- | --- | --- | --- |-----|----- | -----|--|----|
-| NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|crternlog|
-
| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
| -- | -- | --- | --- | ----- | -------- |--| ------ |
| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi |
| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
-| NN | | | | | ..... 01 |m3| crternlog |
+| NN | | | | | ----- 01 |m3| crternlog |
| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask* |
| NN | | | | | 00 011 | | rsvd |
| NN | | | | | 01 011 |0 | svshape |
| NN | | | | | 01 011 |1 | svremap |
| NN | | | | | 10 011 |Rc| svstep |
| NN | | | | | 11 011 |Rc| setvl |
-| NN | | | | | ..... 110 | | 1/2 ops |
+| NN | | | | | ---- 110 | | 1/2 ops |
| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi |
ops (note that av avg and abs as well as vec scalar mask
| NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
| NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
| NN | RT | RA | | 1 | 10 | 0001 110 |Rc| bmatflip |
-| NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv |
+| NN | | | | 1 | 11 | 0001 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm |
| NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm |
| NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm |
| NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop |
-| NN | RT | RA | RB | 0 | | 0101 110 |Rc| rsvd |
+| NN | | | | 0 | | 0101 110 |Rc| rsvd |
| NN | RT | RA | RB | 1 | itype | 0101 110 |Rc| xperm |
| NN | RA | RB | RC | 0 | itype | 1001 110 |Rc| av minmax |
| NN | RA | RB | RC | 1 | 00 | 1001 110 |Rc| av abss |
| NN | RA | RB | RC | 1 | 01 | 1001 110 |Rc| av absu |
| NN | RA | RB | | 1 | 10 | 1001 110 |Rc| av avgadd |
-| NN | RA | RB | | 1 | 11 | 1001 110 |Rc| rsvd |
-| NN | RT | | | | | 1101 110 |Rc| rsvd |
+| NN | | | | 1 | 11 | 1001 110 |Rc| rsvd |
+| NN | RT | RA | RB | 0 | sh | 1101 110 |Rc| shadd |
+| NN | RT | RA | RB | 1 | sh | 1101 110 |Rc| shadduw |
| NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc |
| NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci |
| NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw |
| NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw |
| NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi |
| NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor |
-| NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd |
+| NN | | | | | 10 | --10 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr |
| NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh |
| NN | | | | | | --11 110 |Rc| rsvd |
}
```
+# shift-and-add
+
+Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
+Too complex to add more LD/ST, a compromise is to add shift-and-add.
+Replaces a pair of explicit instructions in hot-loops.
+
+```
+uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+ return (rs1 << (sh+1)) + rs2;
+}
+
+uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+ uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
+ return (rs1z << (sh+1)) + rs2;
+}
+```
+
# cmix
based on RV bitmanip, covered by ternlog bitops
a constant `0b0101...0101` when RA=0, and an option to invert
(including when RA=0, giving a constant 0b1010...1010 as the
initial value) provides a wide range of instructions
-and a means to set regular 64 bit patterns in one
-32 bit instruction.
+and a means to set hundreds of regular 64 bit patterns with one
+single 32 bit instruction.
the two LUT2s are applied left-half (when not swapping)
and right-half (when swapping) so as to allow a wider
Note that if the mask is required to be placed
directly into CR Fields (for use as CR Predicate
-masks rather than a integer mask) then sv.ori
+masks rather than a integer mask) then sv.cmpi or sv.ori
may be used instead, bearing in mind that sv.ori
is a 64-bit instruction, and `VL` must have been
set to the required length:
# grev
+superceded by grevlut
+
based on RV bitmanip, this is also known as a butterfly network. however
where a butterfly network allows setting of every crossbar setting in
every row and every column, generalised-reverse (grev) only allows
```
+# gorc
+
+based on RV bitmanip, gorc is superceded by grevlut
+
+```
+uint32_t gorc32(uint32_t RA, uint32_t RB)
+{
+ uint32_t x = RA;
+ int shamt = RB & 31;
+ if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
+ if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+ return x;
+}
+uint64_t gorc64(uint64_t RA, uint64_t RB)
+{
+ uint64_t x = RA;
+ int shamt = RB & 63;
+ if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
+ ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
+ if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
+ ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
+ ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
+ ((x & 0xFF00FF00FF00FF00LL) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
+ ((x & 0xFFFF0000FFFF0000LL) >> 16);
+ if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
+ ((x & 0xFFFFFFFF00000000LL) >> 32);
+ return x;
+}
+
+```
+
# xperm
based on RV bitmanip.
RA contains a vector of indices to select parts of RB to be
copied to RT. The immediate-variant allows up to an 8 bit
-pattern (repeated) to be targetted at different parts of RT
+pattern (repeated) to be targetted at different parts of RT.
+
+xperm shares some similarity with one of the uses of bmator
+in that xperm indices are binary addressing where bitmator
+may be considered to be unary addressing.
```
uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
{ return xperm(RA, RB, 5); }
```
-# gorc
-
-based on RV bitmanip
+# bitmatrix
```
-uint32_t gorc32(uint32_t RA, uint32_t RB)
+uint64_t bmatflip(uint64_t RA)
{
- uint32_t x = RA;
- int shamt = RB & 31;
- if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
- if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+ uint64_t x = RA;
+ x = shfl64(x, 31);
+ x = shfl64(x, 31);
+ x = shfl64(x, 31);
return x;
}
-uint64_t gorc64(uint64_t RA, uint64_t RB)
+uint64_t bmatxor(uint64_t RA, uint64_t RB)
{
- uint64_t x = RA;
- int shamt = RB & 63;
- if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
- ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
- if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
- ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
- ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
- ((x & 0xFF00FF00FF00FF00LL) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
- ((x & 0xFFFF0000FFFF0000LL) >> 16);
- if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
- ((x & 0xFFFFFFFF00000000LL) >> 32);
+ // transpose of RB
+ uint64_t RBt = bmatflip(RB);
+ uint8_t u[8]; // rows of RA
+ uint8_t v[8]; // cols of RB
+ for (int i = 0; i < 8; i++) {
+ u[i] = RA >> (i*8);
+ v[i] = RBt >> (i*8);
+ }
+ uint64_t x = 0;
+ for (int i = 0; i < 64; i++) {
+ if (pcnt(u[i / 8] & v[i % 8]) & 1)
+ x |= 1LL << i;
+ }
+ return x;
+}
+uint64_t bmator(uint64_t RA, uint64_t RB)
+{
+ // transpose of RB
+ uint64_t RBt = bmatflip(RB);
+ uint8_t u[8]; // rows of RA
+ uint8_t v[8]; // cols of RB
+ for (int i = 0; i < 8; i++) {
+ u[i] = RA >> (i*8);
+ v[i] = RBt >> (i*8);
+ }
+ uint64_t x = 0;
+ for (int i = 0; i < 64; i++) {
+ if ((u[i / 8] & v[i % 8]) != 0)
+ x |= 1LL << i;
+ }
return x;
}
```
+
# Introduction to Carry-less and GF arithmetic
* obligatory xkcd <https://xkcd.com/2595/>
(RT) = r
```
-# bitmatrix
-
-```
-uint64_t bmatflip(uint64_t RA)
-{
- uint64_t x = RA;
- x = shfl64(x, 31);
- x = shfl64(x, 31);
- x = shfl64(x, 31);
- return x;
-}
-uint64_t bmatxor(uint64_t RA, uint64_t RB)
-{
- // transpose of RB
- uint64_t RBt = bmatflip(RB);
- uint8_t u[8]; // rows of RA
- uint8_t v[8]; // cols of RB
- for (int i = 0; i < 8; i++) {
- u[i] = RA >> (i*8);
- v[i] = RBt >> (i*8);
- }
- uint64_t x = 0;
- for (int i = 0; i < 64; i++) {
- if (pcnt(u[i / 8] & v[i % 8]) & 1)
- x |= 1LL << i;
- }
- return x;
-}
-uint64_t bmator(uint64_t RA, uint64_t RB)
-{
- // transpose of RB
- uint64_t RBt = bmatflip(RB);
- uint8_t u[8]; // rows of RA
- uint8_t v[8]; // cols of RB
- for (int i = 0; i < 8; i++) {
- u[i] = RA >> (i*8);
- v[i] = RBt >> (i*8);
- }
- uint64_t x = 0;
- for (int i = 0; i < 64; i++) {
- if ((u[i / 8] & v[i % 8]) != 0)
- x |= 1LL << i;
- }
- return x;
-}
-
-```
-
# Instructions for Binary Galois Fields `GF(2^m)`
see:
projects / libreriscv.git / blobdiff