[[!tag standards]]
+[[!toc levels=1]]
+
# Implementation Log
* ternlogi <https://bugs.libre-soc.org/show_bug.cgi?id=745>
* grev <https://bugs.libre-soc.org/show_bug.cgi?id=755>
* GF2^M <https://bugs.libre-soc.org/show_bug.cgi?id=782>
+
# bitmanipulation
**DRAFT STATUS**
-pseudocode: <https://libre-soc.org/openpower/isa/bitmanip/>
+pseudocode: [[openpower/isa/bitmanip]]
-this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
+this extension amalgamates bitmanipulation primitives from many sources, including RISC-V bitmanip, Packed SIMD, AVX-512 and OpenPOWER VSX.
+Also included are DSP/Multimedia operations suitable for
+Audio/Video. Vectorisation and SIMD are removed: these are straight scalar (element) operations making them suitable for embedded applications.
Vectorisation Context is provided by [[openpower/sv]].
-When combined with SV, scalar variants of bitmanip operations found in VSX are added so that VSX may be retired as "legacy" in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
+When combined with SV, scalar variants of bitmanip operations found in VSX are added so that the Packed SIMD aspects of VSX may be retired as "legacy"
+in the far future (10 to 20 years). Also, VSX is hundreds of opcodes, requires 128 bit pathways, and is wholly unsuited to low power or embedded scenarios.
ternlogv is experimental and is the only operation that may be considered a "Packed SIMD". It is added as a variant of the already well-justified ternlog operation (done in AVX512 as an immediate only) "because it looks fun". As it is based on the LUT4 concept it will allow accelerated emulation of FPGAs. Other vendors of ISAs are buying FPGA companies to achieve similar objectives.
general-purpose Galois Field 2^M operations are added so as to avoid huge custom opcode proliferation across many areas of Computer Science. however for convenience and also to avoid setup costs, some of the more common operations (clmul, crc32) are also added. The expectation is that these operations would all be covered by the same pipeline.
note that there are brownfield spaces below that could incorporate some of the set-before-first and other scalar operations listed in [[sv/vector_ops]], and
-the [[sv/av_opcodes]] as well as [[sv/setvl]]
+the [[sv/av_opcodes]] as well as [[sv/setvl]], [[sv/svstep]], [[sv/remap]]
Useful resource:
| -00 |1 | grevlog |
| -01 | | crternlog |
| 010 |Rc| bitmask |
-| 011 | | gf/cl madd* |
+| 011 | | SVP64 |
| 110 |Rc| 1/2-op |
| 111 | | bmrevi |
TODO: convert all instructions to use RT and not RS
-| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|name|
-| -- | -- | --- | --- | --- |-----|----- | -----|--|----|
-| NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|crternlog|
-
| 0.5|6.10|11.15|16.20 |21..25 | 26....30 |31| name |
| -- | -- | --- | --- | ----- | -------- |--| ------ |
| NN | RT | RA |itype/| im0-4 | im5-7 00 |0 | xpermi |
| NN | RT | RA | RB | im0-4 | im5-7 00 |1 | grevlog |
-| NN | | | | | ..... 01 |0 | crternlog |
+| NN | | | | | ----- 01 |m3| crternlog |
| NN | RT | RA | RB | RC | mode 010 |Rc| bitmask* |
-| NN | RS | RA | RB | RC | 00 011 |0 | gfbmadd |
-| NN | RS | RA | RB | RC | 00 011 |1 | gfbmaddsub |
-| NN | RS | RA | RB | RC | 01 011 |0 | clmadd |
-| NN | RS | RA | RB | RC | 01 011 |1 | clmaddsub |
-| NN | RS | RA | RB | RC | 10 011 |0 | gfpmadd |
-| NN | RS | RA | RB | RC | 10 011 |1 | gfpmaddsub |
-| NN | RS | RA | RB | RC | 11 011 | | rsvd |
+| NN | | | | | 00 011 | | rsvd |
+| NN | | | | | 01 011 |0 | svshape |
+| NN | | | | | 01 011 |1 | svremap |
+| NN | | | | | 10 011 |Rc| svstep |
+| NN | | | | | 11 011 |Rc| setvl |
+| NN | | | | | ---- 110 | | 1/2 ops |
| NN | RT | RA | RB | sh0-4 | sh5 1 111 |Rc| bmrevi |
ops (note that av avg and abs as well as vec scalar mask
| NN | RS | RB | sh | SH | 0 1 | nn00 110 |Rc| bmopsi |
| NN | RT | RA | RB | 1 | 00 | 0001 110 |Rc| cldiv |
| NN | RT | RA | RB | 1 | 01 | 0001 110 |Rc| clmod |
-| NN | RT | RA | RB | 1 | 10 | 0001 110 |Rc| |
-| NN | RT | RB | RB | 1 | 11 | 0001 110 |Rc| clinv |
+| NN | RT | RA | | 1 | 10 | 0001 110 |Rc| bmatflip |
+| NN | | | | 1 | 11 | 0001 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 00 | 0001 110 |Rc| vec sbfm |
| NN | RA | RB | RC | 0 | 01 | 0001 110 |Rc| vec sofm |
| NN | RA | RB | RC | 0 | 10 | 0001 110 |Rc| vec sifm |
| NN | RA | RB | RC | 0 | 11 | 0001 110 |Rc| vec cprop |
+| NN | | | | 0 | | 0101 110 |Rc| rsvd |
| NN | RT | RA | RB | 1 | itype | 0101 110 |Rc| xperm |
-| NN | RA | RB | RC | 0 | itype | 0101 110 |Rc| av minmax |
-| NN | RA | RB | RC | 1 | 00 | 0101 110 |Rc| av abss |
-| NN | RA | RB | RC | 1 | 01 | 0101 110 |Rc| av absu|
-| NN | RA | RB | | 1 | 10 | 0101 110 |Rc| av avgadd |
-| NN | RA | RB | | 1 | 11 | 0101 110 |Rc| rsvd |
-| NN | RA | RB | | | | 1001 110 |Rc| rsvd |
-| NN | RA | RB | | | | 1101 110 |Rc| rsvd |
+| NN | RA | RB | RC | 0 | itype | 1001 110 |Rc| av minmax |
+| NN | RA | RB | RC | 1 | 00 | 1001 110 |Rc| av abss |
+| NN | RA | RB | RC | 1 | 01 | 1001 110 |Rc| av absu |
+| NN | RA | RB | | 1 | 10 | 1001 110 |Rc| av avgadd |
+| NN | | | | 1 | 11 | 1001 110 |Rc| rsvd |
+| NN | RT | RA | RB | 0 | sh | 1101 110 |Rc| shadd |
+| NN | RT | RA | RB | 1 | sh | 1101 110 |Rc| shadduw |
| NN | RA | RB | RC | 0 | 00 | 0010 110 |Rc| gorc |
| NN | RA | RB | sh | SH | 00 | 1010 110 |Rc| gorci |
| NN | RA | RB | RC | 0 | 00 | 0110 110 |Rc| gorcw |
| NN | RA | RB | RC | 0 | 01 | 0110 110 |Rc| grevw |
| NN | RA | RB | sh | 0 | 01 | 1110 110 |Rc| grevwi |
| NN | RA | RB | RC | 1 | 01 | 1110 110 |Rc| bmatxor |
-| NN | RA | RB | RC | | 10 | --10 110 |Rc| rsvd |
+| NN | | | | | 10 | --10 110 |Rc| rsvd |
| NN | RA | RB | RC | 0 | 11 | 1110 110 |Rc| clmulr |
| NN | RA | RB | RC | 1 | 11 | 1110 110 |Rc| clmulh |
-| NN | | | | | | --11 110 |Rc| setvl |
+| NN | | | | | | --11 110 |Rc| rsvd |
# ternlog bitops
| 0.5|6.8 | 9.11|12.14|15.17|18.20|21.28 | 29.30|31|
| -- | -- | --- | --- | --- |-----|----- | -----|--|
-| NN | BT | BA | BB | BC |m0-2 | imm | 10 |m3|
+| NN | BT | BA | BB | BC |m0-2 | imm | 01 |m3|
mask = m0-3,m4
for i in range(4):
- if not mask[i] continue
- crregs[BT][i] = lut3(imm,
- crregs[BA][i],
- crregs[BB][i],
- crregs[BC][i])
+ a,b,c = CRs[BA][i], CRs[BB][i], CRs[BC][i])
+ if mask[i] CRs[BT][i] = lut3(imm, a, b, c)
+# int ops
-# int min/max
+## min/m
-required for
-the [[sv/av_opcodes]]
+required for the [[sv/av_opcodes]]
signed and unsigned min/max for integer. this is sort-of partly synthesiseable in [[sv/svp64]] with pred-result as long as the dest reg is one of the sources, but not both signed and unsigned. when the dest is also one of the srces and the mv fails due to the CR bittest failing this will only overwrite the dest where the src is greater (or less).
}
```
+## average
+
+required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
+but not scalar
+
+```
+uint_xlen_t intavg(uint_xlen_t rs1, uint_xlen_t rs2) {
+ return (rs1 + rs2 + 1) >> 1:
+}
+```
+
+## abs
+
+required for the [[sv/av_opcodes]], these exist in Packed SIMD (VSX)
+but not scalar
+
+```
+uint_xlen_t intabs(uint_xlen_t rs1, uint_xlen_t rs2) {
+ return (src1 > src2) ? (src1-src2) : (src2-src1)
+}
+```
+
+# shift-and-add
+
+Power ISA is missing LD/ST with shift, which is present in both ARM and x86.
+Too complex to add more LD/ST, a compromise is to add shift-and-add.
+Replaces a pair of explicit instructions in hot-loops.
+
+```
+uint_xlen_t shadd(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+ return (rs1 << (sh+1)) + rs2;
+}
+
+uint_xlen_t shadduw(uint_xlen_t rs1, uint_xlen_t rs2, uint8_t sh) {
+ uint_xlen_t rs1z = rs1 & 0xFFFFFFFF;
+ return (rs1z << (sh+1)) + rs2;
+}
+```
-## cmix
+# cmix
based on RV bitmanip, covered by ternlog bitops
a constant `0b0101...0101` when RA=0, and an option to invert
(including when RA=0, giving a constant 0b1010...1010 as the
initial value) provides a wide range of instructions
-and a means to set regular 64 bit patterns in one
-32 bit instruction.
+and a means to set hundreds of regular 64 bit patterns with one
+single 32 bit instruction.
the two LUT2s are applied left-half (when not swapping)
and right-half (when swapping) so as to allow a wider
Note that if the mask is required to be placed
directly into CR Fields (for use as CR Predicate
-masks rather than a integer mask) then sv.ori
+masks rather than a integer mask) then sv.cmpi or sv.ori
may be used instead, bearing in mind that sv.ori
is a 64-bit instruction, and `VL` must have been
set to the required length:
# grev
+superceded by grevlut
+
based on RV bitmanip, this is also known as a butterfly network. however
where a butterfly network allows setting of every crossbar setting in
every row and every column, generalised-reverse (grev) only allows
```
+# gorc
+
+based on RV bitmanip, gorc is superceded by grevlut
+
+```
+uint32_t gorc32(uint32_t RA, uint32_t RB)
+{
+ uint32_t x = RA;
+ int shamt = RB & 31;
+ if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
+ if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+ return x;
+}
+uint64_t gorc64(uint64_t RA, uint64_t RB)
+{
+ uint64_t x = RA;
+ int shamt = RB & 63;
+ if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
+ ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
+ if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
+ ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
+ if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
+ ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
+ if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
+ ((x & 0xFF00FF00FF00FF00LL) >> 8);
+ if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
+ ((x & 0xFFFF0000FFFF0000LL) >> 16);
+ if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
+ ((x & 0xFFFFFFFF00000000LL) >> 32);
+ return x;
+}
+
+```
+
# xperm
based on RV bitmanip.
RA contains a vector of indices to select parts of RB to be
copied to RT. The immediate-variant allows up to an 8 bit
-pattern (repeated) to be targetted at different parts of RT
+pattern (repeated) to be targetted at different parts of RT.
+
+xperm shares some similarity with one of the uses of bmator
+in that xperm indices are binary addressing where bitmator
+may be considered to be unary addressing.
```
uint_xlen_t xpermi(uint8_t imm8, uint_xlen_t RB, int sz_log2)
{ return xperm(RA, RB, 5); }
```
-# gorc
-
-based on RV bitmanip
+# bitmatrix
```
-uint32_t gorc32(uint32_t RA, uint32_t RB)
+uint64_t bmatflip(uint64_t RA)
{
- uint32_t x = RA;
- int shamt = RB & 31;
- if (shamt & 1) x |= ((x & 0x55555555) << 1) | ((x & 0xAAAAAAAA) >> 1);
- if (shamt & 2) x |= ((x & 0x33333333) << 2) | ((x & 0xCCCCCCCC) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F) << 4) | ((x & 0xF0F0F0F0) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF) << 8) | ((x & 0xFF00FF00) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF) << 16) | ((x & 0xFFFF0000) >> 16);
+ uint64_t x = RA;
+ x = shfl64(x, 31);
+ x = shfl64(x, 31);
+ x = shfl64(x, 31);
return x;
}
-uint64_t gorc64(uint64_t RA, uint64_t RB)
+uint64_t bmatxor(uint64_t RA, uint64_t RB)
{
- uint64_t x = RA;
- int shamt = RB & 63;
- if (shamt & 1) x |= ((x & 0x5555555555555555LL) << 1) |
- ((x & 0xAAAAAAAAAAAAAAAALL) >> 1);
- if (shamt & 2) x |= ((x & 0x3333333333333333LL) << 2) |
- ((x & 0xCCCCCCCCCCCCCCCCLL) >> 2);
- if (shamt & 4) x |= ((x & 0x0F0F0F0F0F0F0F0FLL) << 4) |
- ((x & 0xF0F0F0F0F0F0F0F0LL) >> 4);
- if (shamt & 8) x |= ((x & 0x00FF00FF00FF00FFLL) << 8) |
- ((x & 0xFF00FF00FF00FF00LL) >> 8);
- if (shamt & 16) x |= ((x & 0x0000FFFF0000FFFFLL) << 16) |
- ((x & 0xFFFF0000FFFF0000LL) >> 16);
- if (shamt & 32) x |= ((x & 0x00000000FFFFFFFFLL) << 32) |
- ((x & 0xFFFFFFFF00000000LL) >> 32);
+ // transpose of RB
+ uint64_t RBt = bmatflip(RB);
+ uint8_t u[8]; // rows of RA
+ uint8_t v[8]; // cols of RB
+ for (int i = 0; i < 8; i++) {
+ u[i] = RA >> (i*8);
+ v[i] = RBt >> (i*8);
+ }
+ uint64_t x = 0;
+ for (int i = 0; i < 64; i++) {
+ if (pcnt(u[i / 8] & v[i % 8]) & 1)
+ x |= 1LL << i;
+ }
+ return x;
+}
+uint64_t bmator(uint64_t RA, uint64_t RB)
+{
+ // transpose of RB
+ uint64_t RBt = bmatflip(RB);
+ uint8_t u[8]; // rows of RA
+ uint8_t v[8]; // cols of RB
+ for (int i = 0; i < 8; i++) {
+ u[i] = RA >> (i*8);
+ v[i] = RBt >> (i*8);
+ }
+ uint64_t x = 0;
+ for (int i = 0; i < 64; i++) {
+ if ((u[i / 8] & v[i % 8]) != 0)
+ x |= 1LL << i;
+ }
return x;
}
```
-# Introductory Explanation for Carry-less and Gallois Field
-There are three completely separate types of Galois Field
-arithmetic which are not well explained even in introductory
-literature.
-
-* GF(2) which is covered by bibary XOR
-
-# Instructions for Carry-less Operations aka. Polynomials with coefficients in `GF(2)`
+# Introduction to Carry-less and GF arithmetic
+
+* obligatory xkcd <https://xkcd.com/2595/>
+
+There are three completely separate types of Galois-Field-based
+arithmetic that we implement which are not well explained even in introductory literature. A slightly oversimplified explanation
+is followed by more accurate descriptions:
+
+* `GF(2)` carry-less binary arithmetic. this is not actually a Galois Field,
+ but is accidentally referred to as GF(2) - see below as to why.
+* `GF(p)` modulo arithmetic with a Prime number, these are "proper" Galois Fields
+* `GF(2^N)` carry-less binary arithmetic with two limits: modulo a power-of-2
+ (2^N) and a second "reducing" polynomial (similar to a prime number), these
+ are said to be GF(2^N) arithmetic.
+
+further detailed and more precise explanations are provided below
+
+* **Polynomials with coefficients in `GF(2)`**
+ (aka. Carry-less arithmetic -- the `cl*` instructions).
+ This isn't actually a Galois Field, but its coefficients are. This is
+ basically binary integer addition, subtraction, and multiplication like
+ usual, except that carries aren't propagated at all, effectively turning
+ both addition and subtraction into the bitwise xor operation. Division and
+ remainder are defined to match how addition and multiplication works.
+* **Galois Fields with a prime size**
+ (aka. `GF(p)` or Prime Galois Fields -- the `gfp*` instructions).
+ This is basically just the integers mod `p`.
+* **Galois Fields with a power-of-a-prime size**
+ (aka. `GF(p^n)` or `GF(q)` where `q == p^n` for prime `p` and
+ integer `n > 0`).
+ We only implement these for `p == 2`, called Binary Galois Fields
+ (`GF(2^n)` -- the `gfb*` instructions).
+ For any prime `p`, `GF(p^n)` is implemented as polynomials with
+ coefficients in `GF(p)` and degree `< n`, where the polynomials are the
+ remainders of dividing by a specificly chosen polynomial in `GF(p)` called
+ the Reducing Polynomial (we will denote that by `red_poly`). The Reducing
+ Polynomial must be an irreducable polynomial (like primes, but for
+ polynomials), as well as have degree `n`. All `GF(p^n)` for the same `p`
+ and `n` are isomorphic to each other -- the choice of `red_poly` doesn't
+ affect `GF(p^n)`'s mathematical shape, all that changes is the specific
+ polynomials used to implement `GF(p^n)`.
+
+Many implementations and much of the literature do not make a clear
+distinction between these three categories, which makes it confusing
+to understand what their purpose and value is.
+
+* carry-less multiply is extremely common and is used for the ubiquitous
+ CRC32 algorithm. [TODO add many others, helps justify to ISA WG]
+* GF(2^N) forms the basis of Rijndael (the current AES standard) and
+ has significant uses throughout cryptography
+* GF(p) is the basis again of a significant quantity of algorithms
+ (TODO, list them, jacob knows what they are), even though the
+ modulo is limited to be below 64-bit (size of a scalar int)
+
+# Instructions for Carry-less Operations
+
+aka. Polynomials with coefficients in `GF(2)`
Carry-less addition/subtraction is simply XOR, so a `cladd`
instruction is not provided since the `xor[i]` instruction can be used instead.
These are operations on polynomials with coefficients in `GF(2)`, with the
polynomial's coefficients packed into integers with the following algorithm:
-[[!inline pagenames="openpower/sv/bitmanip/pack_poly.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/pack_poly.py" raw="yes"]]
+```
## Carry-less Multiply Instructions
### `clmul` Carry-less Multiply
-[[!inline pagenames="openpower/sv/bitmanip/clmul.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/clmul.py" raw="yes"]]
+```
### `clmulh` Carry-less Multiply High
-[[!inline pagenames="openpower/sv/bitmanip/clmulh.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/clmulh.py" raw="yes"]]
+```
### `clmulr` Carry-less Multiply (Reversed)
Useful for CRCs. Equivalent to bit-reversing the result of `clmul` on
bit-reversed inputs.
-[[!inline pagenames="openpower/sv/bitmanip/clmulr.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/clmulr.py" raw="yes"]]
+```
## `clmadd` Carry-less Multiply-Add
`cldivrem` isn't an actual instruction, but is just used in the pseudo-code
for other instructions.
-[[!inline pagenames="openpower/sv/bitmanip/cldivrem.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/cldivrem.py" raw="yes"]]
+```
## `cldiv` Carry-less Division
making it reducible, making whatever we're working on no longer a Field.
Therefore, we can reuse the LSB to indicate `degree == XLEN`.
-[[!inline pagenames="openpower/sv/bitmanip/decode_reducing_polynomial.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/decode_reducing_polynomial.py" raw="yes"]]
+```
## `gfbredpoly` -- Set the Reducing Polynomial SPR `GFBREDPOLY`
unless this is an immediate op, `mtspr` is completely sufficient.
-[[!inline pagenames="openpower/sv/bitmanip/gfbredpoly.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfbredpoly.py" raw="yes"]]
+```
## `gfbmul` -- Binary Galois Field `GF(2^m)` Multiplication
gfbmul RT, RA, RB
```
-[[!inline pagenames="openpower/sv/bitmanip/gfbmul.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfbmul.py" raw="yes"]]
+```
## `gfbmadd` -- Binary Galois Field `GF(2^m)` Multiply-Add
gfbmadd RT, RA, RB, RC
```
-[[!inline pagenames="openpower/sv/bitmanip/gfbmadd.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfbmadd.py" raw="yes"]]
+```
## `gfbtmadd` -- Binary Galois Field `GF(2^m)` Twin Multiply-Add (for FFT)
gfbinv RT, RA
```
-[[!inline pagenames="openpower/sv/bitmanip/gfbinv.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfbinv.py" raw="yes"]]
+```
# Instructions for Prime Galois Fields `GF(p)`
gfpadd RT, RA, RB
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpadd.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpadd.py" raw="yes"]]
+```
the addition happens on infinite-precision integers
gfpsub RT, RA, RB
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpsub.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpsub.py" raw="yes"]]
+```
the subtraction happens on infinite-precision integers
gfpmul RT, RA, RB
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpmul.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpmul.py" raw="yes"]]
+```
the multiplication happens on infinite-precision integers
Some potential hardware implementations are found in:
<https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.90.5233&rep=rep1&type=pdf>
-[[!inline pagenames="openpower/sv/bitmanip/gfpinv.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpinv.py" raw="yes"]]
+```
## `gfpmadd` Prime Galois Field `GF(p)` Multiply-Add
gfpmadd RT, RA, RB, RC
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpmadd.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpmadd.py" raw="yes"]]
+```
the multiplication and addition happens on infinite-precision integers
gfpmsub RT, RA, RB, RC
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpmsub.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpmsub.py" raw="yes"]]
+```
the multiplication and subtraction happens on infinite-precision integers
gfpmsubr RT, RA, RB, RC
```
-[[!inline pagenames="openpower/sv/bitmanip/gfpmsubr.py" raw="true" feeds="no" actions="yes"]]
+```python
+[[!inline pagenames="gf_reference/gfpmsubr.py" raw="yes"]]
+```
the multiplication and subtraction happens on infinite-precision integers
(RS) = gfpmsubr(factor1, factor2, term)
```
-# bitmatrix
-
-```
-uint64_t bmatflip(uint64_t RA)
-{
- uint64_t x = RA;
- x = shfl64(x, 31);
- x = shfl64(x, 31);
- x = shfl64(x, 31);
- return x;
-}
-uint64_t bmatxor(uint64_t RA, uint64_t RB)
-{
- // transpose of RB
- uint64_t RBt = bmatflip(RB);
- uint8_t u[8]; // rows of RA
- uint8_t v[8]; // cols of RB
- for (int i = 0; i < 8; i++) {
- u[i] = RA >> (i*8);
- v[i] = RBt >> (i*8);
- }
- uint64_t x = 0;
- for (int i = 0; i < 64; i++) {
- if (pcnt(u[i / 8] & v[i % 8]) & 1)
- x |= 1LL << i;
- }
- return x;
-}
-uint64_t bmator(uint64_t RA, uint64_t RB)
-{
- // transpose of RB
- uint64_t RBt = bmatflip(RB);
- uint8_t u[8]; // rows of RA
- uint8_t v[8]; // cols of RB
- for (int i = 0; i < 8; i++) {
- u[i] = RA >> (i*8);
- v[i] = RBt >> (i*8);
- }
- uint64_t x = 0;
- for (int i = 0; i < 64; i++) {
- if ((u[i / 8] & v[i % 8]) != 0)
- x |= 1LL << i;
- }
- return x;
-}
-
-```
-
# Already in POWER ISA
## count leading/trailing zeros with mask
## bit deposit
-vpdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
+pdepd VRT,VRA,VRB, identical to RV bitmamip bdep, found already in v3.1 p106
do while(m < 64)
if VSR[VRB+32].dword[i].bit[63-m]=1 then do
```
-# bit extract
+## bit extract
-other way round: identical to RV bext, found in v3.1 p196
+other way round: identical to RV bext: pextd, found in v3.1 p196
```
uint_xlen_t bext(uint_xlen_t RA, uint_xlen_t RB)
}
```
-# centrifuge
+## centrifuge
found in v3.1 p106 so not to be added here
RA = result
```
-# bit to byte permute
+## bit to byte permute
similar to matrix permute in RV bitmanip, which has XOR and OR variants,
-these perform a transpose.
+these perform a transpose. TODO this looks VSX is there a scalar variant
+in v3.0/1 already
do j = 0 to 7
do k = 0 to 7
b = VSR[VRB+32].dword[i].byte[k].bit[j]
VSR[VRT+32].dword[i].byte[j].bit[k] = b
+# Appendix
+
+see [[bitmanip/appendix]]
+
projects / libreriscv.git / blobdiff