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[libreriscv.git] / openpower / sv / branches.mdwn

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 75836fed7b83a63983ce6a5187859ea1db1dd15e..554a90924cbc3d12202319ae8055c7774c174900 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -79,10 +79,24 @@ which may be enabled and combined):
   CTR is decremented, including options to decrement if a Condition
   test succeeds *or if it fails*.
 
+With these side-effects, basic Boolean Logic Analysis advises thay
+it is important to provide a means
+to enact them each based on whether testing succeeds *or fails*. This
+results in a not-insignificant number of additional Mode Augmentation bits,
+accompanying VLSET and CTR-test Modes respectively.
+
 It is also important to note that Vectorised Branches can be used
 in either SVP64 Horizontal-First or Vertical-First Mode. Essentially
 the behaviour is identical in both Modes.
 
+It is also important
+to bear in mind that, fundamentally, Vectorised Branch-Conditional
+is still extremely close to the Scalar v3.0B Branch-Conditional
+instructions, and that the same v3.0B Scalar Branch-Conditional
+instructions are still
+*completely separate and independent*, being unaltered and
+unaffected by their SVP64 variants in every conceivable way.
+
 # Format and fields
 
 SVP64 RM `MODE` (includes `ELWIDTH` and `ELWIDTH_SRC` bits) for Branch
@@ -123,7 +137,12 @@ Brief description of fields:
   tested. CTR inversion decrements if a test *fails*. Only relevant
   in CTR-test Mode.
 
-# Description and Modes
+# Vectorised CR Field numbering, and Scalar behaviour
+
+It is important to keep in mind that just like all SVP64 instructions,
+the `BI` field of the base v3.0B Branch Conditional instruction
+may be extended by SVP64 EXTRA augmentation, as well as be marked
+as either Scalar or Vector.
 
 The `BI` field of Branch Conditional operations is five bits, in scalar
 v3.0B this would select one bit of the 32 bit CR,
@@ -134,13 +153,21 @@ are extended to either scalar or vector and to select CR Fields 0..127
 as specified in SVP64 [[sv/svp64/appendix]].
 
 When the CR Fields selected by SVP64-Augmented `BI` is marked as scalar,
-then as the usual SVP64 rules apply,
+then as the usual SVP64 rules apply:
 the loop ends at the first element tested, after taking
 predication into consideration. Thus, also as usual, when a predicate mask is
 given, and `BI` marked as scalar, and `sz` is zero, srcstep
 skips forward to the first non-zero predicated element, and only that
 one element is tested.
 
+In other words, the fact that this is a Branch
+Operation (instead of an arithmetic one) does not result, ultimately,
+in significant changes as to
+how SVP64 is fundamentally applied, except with respect to early-out
+opportunities and CTR-testing, which are outlined below.
+
+# Description and Modes
+
 In SVP64 Horizontal-First Mode, the first failure in ALL mode (Great Big
 AND) results in early exit: no more updates to CTR occur (if requested);
 no branch occurs, and LR is not updated (if requested). Likewise for