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[libreriscv.git] / openpower / sv / branches.mdwn

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index cc9b91bd357efb6fc52caf460220f2e51a25bc47..d4487dba9b0d077ee128e2883df3301dcc3316be 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -91,8 +91,9 @@ Predication in both INT and CR modes may be applied to `sv.bc` and other
 SVP64 Branch Conditional operations, exactly as they may be applied to
 other SVP64 operations.  When `sz` is zero, any masked-out Branch-element
 operations are not included in condition testing, exactly like all other
-SVP64 operations. With one exception this *includes* side-effects such as potentially updating
-LR and CTR which will also be skipped. The exception here is when
+SVP64 operations, *including* side-effects such as potentially updating
+LR or CTR, which will also be skipped. There is *one* exception here,
+which is when
 `BO[2]=0, sz=0, CTR-test=0, CTi=1` and the relevant element
 predicate mask bit is also zero:
 under these special circumstances CTR will also decrement.