fix fcvttg* overflow/FPSCR computation

[libreriscv.git] / openpower / sv / byteswap.mdwn

diff --git a/openpower/sv/byteswap.mdwn b/openpower/sv/byteswap.mdwn
index d867f5588ed4c31a1e63b36467aebe71900b3e6c..6fd96e228c7b21a90b383c2f49f14cd1e6baca9b 100644 (file)
--- a/openpower/sv/byteswap.mdwn
+++ b/openpower/sv/byteswap.mdwn
@@ -1,9 +1,15 @@
+[[!tag standards]]
+
 # Byte-swapping
 
 ## Byte-swapping Mux
 
+gate count for 4:1 MUX is estimated at 8 gates.  8x 64 gates for a total of 512 gates to provide aligned byteswapping 64 bit. (actually likely 5x64 for MUX part and 2x8 for selection part)
+
 <img alt="Byte-swap mux diagram" src="../byteswap_mux.svg" width="100%"/>
 
 ## Byte-swapping Pipe
 
-<img alt="Byte-swap pipe diagram" src="../byteswap_pipe.svg" width="100%"/>
\ No newline at end of file
+per source and dest operand, 512 gates required.  if two source operands (ALU pipeline, Logical pipeline) this totals 1600 gates (per Function Unit).  3 operands (madd) is 2000 gates.  for an estimated 50 Function Units this totals around 100,000 gates.
+
+<img alt="Byte-swap pipe diagram" src="../byteswap_pipe.svg" width="100%"/>