more clarification

[libreriscv.git] / openpower / sv / comparison_table.mdwn

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index 712ad7f161e9eaf93d55b36c19a577bd7c9c9291..3925e82a90d5c634f683d61ea2b8fdf3a62fbf92 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -15,7 +15,7 @@
 * (3): on specific operations.  See [[opcode_regs_deduped]] for full list. Key: 2P - Twin Predication, 1P - Single-Predicate
 * (4): SVP64 provides a Vector concept on top of the **Scalar** GPR, FPR and CR Fields, extended to 128 entries.
 * (5): SVP64 Vectorises Scalar ops. It is up to the **implementor** to choose (**optionally**) whether to apply SVP64 to e.g. VSX Quad-Precision (128-bit) instructions, to create 128-bit Vector ops.
-* (6): big-integer add is just `sv.adde`. Bigint Mul and divide require addition of two scalar operations. See [[sv/biginteger/analysis]]
+* (6): big-integer add is just `sv.adde`. For optimal performance Bigint Mul and divide first require addition of two scalar operations (which are then naturally Vectorised by SVP64). See [[sv/biginteger/analysis]]
 * (7): See [[sv/svp64/appendix]] and [ARM SVE Fault-First](https://alastairreid.github.io/papers/sve-ieee-micro-2017.pdf)
 * (8): Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
 * (9): Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]