fix fcvttg* overflow/FPSCR computation

[libreriscv.git] / openpower / sv / compliancy_levels.mdwn

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index ef48df058afdd7ae72a0a52a9e97cffb0c8b3d83..577cde76e5ddbe80e99542d6a81171720631aa7a 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -1,5 +1,3 @@
-[[!tag standards]]
-
 # Simple-V Compliancy Levels
 
 The purpose of the Compliancy Levels is to provide a documented
@@ -29,6 +27,9 @@ instruction deviate from the Scalar Power ISA Specification.
 
 Summary of Compliancy Levels, each Level includes all lower levels:
 
+* **Zero-Level**: Simple-V is not implemented (at all) in hardware. This
+  Level is required to be listed because all capabilities of Simple-V
+  must be Soft-emulatable.
 * **Ultra-embedded**: `setvl` instruction and context-switching of SVSTATE
   to/from SVSRR1. Register Files as Standard Power ISA. `scalar identity`
   implemented.
@@ -36,10 +37,12 @@ Summary of Compliancy Levels, each Level includes all lower levels:
   and support for Hardware for-looping
   in both Horizontal-First and Vertical-First Mode as well as Predication
   (Single and Twin) for the GPRs r3, r10 and r30.  CR-Field-based
-  Predicates, if used, may still raise illegal instruction trap.
-* **DSP/AV**: 128 registers,
+  Predicates do not need to be added.
+* **Embedded DSP/AV**: 128 registers,
    element-width
   overrides, and Saturation and Mapreduce/Iteration Modes.
+* **High-end DSP/AV**: Same as Embedded-DSP/AV except also
+  including Indexed and Offset REMAP capability.
 * **3D/Advanced/Supercomputing**:  all SV Branch instructions;
   crweird and vector-assist instructions (`set-before-first` etc);
   Swizzle Move instructions;
@@ -62,7 +65,19 @@ The SV Compliancy Levels have nothing to do with the Power ISA Compliancy
 Levels (SFS, SFFS, Linux, AIX). They are separate and independent. It
 is perfectly fine to implement Ultra-Embedded on AIX, and perfectly fine to implement 3D/Advanced on SFS. **Compliance with SV Levels does not convey or remove the obligation of Compliance with SFS/SFFS/Linux/AIX Levels and vice-versa**.
 
-# Ultra-Embedded Level
+## Zero-Level
+
+This level exists to indicate the critical importance of all and any
+features attempted to be executed on hardware that has no support at
+all for Simple-V being **required** to raise Illegal Exceptions.
+**This includes existing Power ISA Implementations:** IBM POWER being
+the most notable.
+
+With parts of the Power ISA being "silent executed" (hints for example),
+it is absolutely critical to have all capabilities of Simple-V sit
+within full Illegal Instruction space of existing and future Hardware.
+
+## Ultra-Embedded Level
 
 This level exists as an entry-level into SVP64, most suited to resource
 constrained soft cores, or Hardware implementations where unit cost is a much
@@ -101,7 +116,7 @@ an SVP64 Prefixed instruction is identical in every respect to
 Scalar non-prefixed, i.e. as if the Prefix had not been present.
 Additionally all SV SPRs must be zero and the 24-bit `RM` field must be zero.
 
-# Embedded Level
+## Embedded Level
 
 This level is more suitable for Hardware implementations where performance and power saving begins to matter.  A second instruction, `svstep`, used
 by Vertical-First Mode, is required, as is hardware-level looping in
@@ -134,7 +149,7 @@ modifying the Scalar Power ISA.  The cost in software is that Predicated
 instructions are Prefixed
 to 64-bit.
 
-# DSP / Audio / Video Level
+## DSP / Audio / Video Level
 
 This level is best suited to high-performance power-efficient but
 specialist Compute workloads.  128 GPRs, FPRs and CR Fields are all
@@ -147,11 +162,19 @@ All SVP64 Modes must be implemented in hardware: Saturation
 in particular is a necessity for Audio DSP work. Reduction as well to
 assist with Audio/Video.
 
-It is not mandatory for this Level to have DCT/FFT REMAP Capability but
+It is not mandatory for this Level to have DCT/FFT REMAP Capability in
+hardware but
 due to the high prevalence of DCT and FFT in Audio, Video and DSP
-workloads it is strongly recommended.
+workloads it is strongly recommended. Matrix (Dimensional) REMAP
+and Swizzle may also be useful to help with 24-bit (3 byte) Structured Audio Streams and are also recommended but not mandatory.
+
+## High-end DSP
 
-# 3D / Advanced / Supercomputing
+In this Compliancy Level the benefits of the Offset and Index REMAP
+subsystem becomes worth its hardware cost.  In lower-performing DSP
+and A/V workloads it is not.
+
+## 3D / Advanced / Supercomputing
 
 This Compliancy Level is for highest performance and energy efficiency.
 All aspects of SVP64 must be entirely implemented, in full, in Hardware.
@@ -167,7 +190,7 @@ additional Register Hazard Dependencies on fine-grained (8/16/32-bit)
 operations.  Just as with SRAMs multiple write-enable lines may be
 raised to update higher-width elements.
 
-# Examples
+## Examples
 
 Assuming that hardware implements scalar operations only,
 and implements predication but not elwidth overrides:
@@ -185,7 +208,14 @@ elwidth overrides if requested always raise illegal instruction
 traps.
 
 Such an implementation would qualify for the "Ultra-Embedded" SV Level.
-It would not qualify for the "Embedded" level because when VL=1 an
+It would not qualify for the "Embedded" level because when VL=4 an
 Illegal Exception is raised, and the Embedded Level requires full
 VL Loop support in hardware.
 
+[[!tag standards]]
+
+-------
+
+\newpage{}
+
+