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[libreriscv.git] / openpower / sv / cr_int_predication.mdwn

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index fee9ee97373dcd52d76994123505d9a6c1d2e5c4..0c1dd88e22c0c047724adcd07c5dd59c0c79f99a 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -10,11 +10,89 @@ Basic concept:
   of a CR to create a single bit value (0/1) in an integer register
 * Inverse of the same, taking a single bit value (0/1) from an integer
   register to selectively target all four bits of a given CR
+* CR-to-CR version of the same, allowing multiple bits to be AND/OR/XORed
+  in one hit.
 * Vectorisation of the same
 
 Purpose:
 
 * To provide a merged version of what is currently a multi-sequence of
-  CR operations (crand, cror, crxor) with mfcr and mtcrf
+  CR operations (crand, cror, crxor) with mfcr and mtcrf, reducing
+  instruction count.
 * To provide a vectorised version of the same, suitable for advanced
   predication
+
+Side-effects:
+
+* mtcrweird when RA=0 is a means to set or clear arbitrary CR bits from immediates
+
+(Twin) Predication interactions:
+
+* INT twin predication with zeroing is a way to copy an integer into CRs without necessarily needing the INT register (RA).  if it is, it is effectively ANDed (or negate-and-ANDed) with the INT Predicate
+* CR twin predication with zeroing is likewise a way to interact with the incoming integer
+
+this gets particularly powerful if data-dependent predication is also enabled.
+
+# Instruction form and pseudocode
+
+    | 0-5 | 6-10  | 11 | 12-15 | 16-18 | 19-20 | 21-25   | 26-30   | 31 |
+    | --- | ----  | -- | ----- | ----- | ----- | -----   | -----   | -- |
+    | 19  | RT    |    | mask  | BB    |    /  | XO[0:4] | XO[5:9] | /  |
+    | 19  | RT    | 0  | mask  | BB    |  0 /  | XO[0:4] | 0 mode  | /  |
+    | 19  | RA    | 1  | mask  | BB    |  0 /  | XO[0:4] | 0 mode  | /  |
+    | 19  | BT // | 0  | mask  | BB    |  1 /  | XO[0:4] | 0 mode  | /  |
+    | 19  | BFT   | 1  | mask  | BB    |  1 /  | XO[0:4] | 0 mode  | /  |
+
+mode is encoded in XO and is 4 bits
+
+bit 11=0, bit 19=0
+
+    crrweird: RT, BB, mask.mode
+
+    creg = CRfile[32+BB*4:36+BB*4]
+    n0 = mask[0] & (mode[0] == creg[0])
+    n1 = mask[1] & (mode[1] == creg[1])
+    n2 = mask[2] & (mode[2] == creg[2])
+    n3 = mask[3] & (mode[3] == creg[3])
+    RT[0] = n0|n1|n2|n3
+
+bit 11=1, bit 19=0
+
+    mtcrweird: RA, BB, mask.mode
+
+    reg = (RA|0)
+    n0 = mask[0] & (mode[0] == reg[0])
+    n1 = mask[1] & (mode[1] == reg[0])
+    n2 = mask[2] & (mode[2] == reg[0])
+    n3 = mask[3] & (mode[3] == reg[0])
+    CRfile[32+BB*4:36+BB*4] = n0 || n1 || n2 || n3
+
+bit 11=0, bit 19=1
+
+    crweird: BT, BB, mask.mode
+
+    creg = CRfile[32+BB*4:36+BB*4]
+    n0 = mask[0] & (mode[0] == creg[0])
+    n1 = mask[1] & (mode[1] == creg[1])
+    n2 = mask[2] & (mode[2] == creg[2])
+    n3 = mask[3] & (mode[3] == creg[3])
+    CRfile[32+BT*4:36+BT*4] = n0 || n1 || n2 || n3
+
+bit 11=1, bit 19=1
+
+    crweirder: BFT, BB, mask.mode
+
+    creg = CRfile[32+BB*4:36+BB*4]
+    n0 = mask[0] & (mode[0] == creg[0])
+    n1 = mask[1] & (mode[1] == creg[1])
+    n2 = mask[2] & (mode[2] == creg[2])
+    n3 = mask[3] & (mode[3] == creg[3])
+    CRfile[32+BFT] = n0|n1|n2|n3
+
+Pseudo-op:
+
+    mtcri BB, mode    mtcrweird r0, BB, 0b1111.~mode
+    mtcrset BB, mask  mtcrweird r0, BB, mask.0b0000
+    mtcrclr BB, mask  mtcrweird r0, BB, mask.0b1111
+
+