bit-level packing descriptions for crweird family of instructions

[libreriscv.git] / openpower / sv / cr_int_predication.mdwn

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 27a24a641342374891f2f7b41493cf763ad36001..26958dd4ca2ae300e93f06badcdca4b4b6c5d4e6 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -90,9 +90,9 @@ OPF ISA WG):
 |---|---- |--|-----|-----|-----|-----  |-----  |--|----      |
 |19 |RT   |  |mask |BFA  |     |XO[0:4]|XO[5:9]|/ |          |
 |19 |     |  |     |     |     |1 //// |00011  |  |rsvd      |
-|19 |RT   |M |mask |BFA  | 0 0 |0 mode |00011  |0 |crrweird  |
-|19 |RT   |0 |mask |BFA  | 0 0 |0 mode |00011  |1 |mfcrweird |
-|19 |RA   |1 |mask |BF   | 0 0 |0 mode |00011  |1 |mtcrrweird |
+|19 |RT   |M |mask |BFA  | 0 0 |1 mode |00011  |Rc|crrweird  |
+|19 |RT   |M |mask |BFA  | 0 1 |1 mode |00011  |Rc|mfcrweird |
+|19 |RA   |M |mask |BF   | 0 0 |0 mode |00011  |1 |mtcrrweird |
 |19 |RA   |M |mask |BF   | 0 1 |0 mode |00011  |0 |mtcrweird |
 |19 |BT   |M |mask |BFA  | 0 1 |0 mode |00011  |1 |crweirder |
 |19 |BF //|M |mask |BFA  | 1 1 |0 mode |00011  |0 |crweird   |
@@ -113,11 +113,33 @@ bit 19=0, bit 20=0
     n3 = mask[3] & (mode[3] == creg[3])
     result = n0|n1|n2|n3 if M else n0&n1&n2&n3
     RT[63] = result # MSB0 numbering, 63 is LSB
+    If Rc:
+        CR0 = analyse(RT)
 
 When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
-SVP64 type operation and as such can use RC1 Data-dependent
+SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
 Mode capability
 
+Also as noted below, element-width override bits normally used
+on the source is instead used to allow multiple results to be packed
+sequentially into the destination. *Destination elwidth overrides still apply*
+
+When the destination elwidth is default (0b00) the following packing occurs
+into destination elements:
+
+- SVRM bits 6:7 equal to 0b00 - one result element packed into one bit of each
+  destination element (in the LSB)
+- SVRM bits 6:7 equal to 0b01 - two result elements packed into two bits of
+  destination element (in the bottom two LSBs)
+- SVRM bits 6:7 equal to 0b10 - four result elements packed into four bits of
+  destination element (in the bottom four LSBs)
+- SVRM bits 6:7 equal to 0b11 - eight result elements packed into four bits of
+  destination element (in the bottom four LSBs)
+
+When for example the destination elwidth is 8-bit (0b11) then the destination
+element widths are 8-bit, and the result elements (grouped up to 8) still fit
+neatly into each 8-bit destination element.
+
 **mfcrrweird**
 
 mode is encoded in XO and is 4 bits
@@ -133,10 +155,35 @@ bit 19=0, bit 20=0
     n3 = mask[3] & (mode[3] == creg[3])
     result = n0||n1||n2||n3
     RT[60:63] = result # MSB0 numbering, 63 is LSB
+    If Rc:
+        CR0 = analyse(RT)
 
 When used with SVP64 Prefixing this is a [[openpower/sv/normal]]
-SVP64 type operation and as such can use RC1 Data-dependent
-Mode capability
+SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
+Mode capability.
+
+Also as noted below, element-width override bits normally used
+on the source is instead used to allow multiple results to be packed
+into the destination.  *Destination elwidth overrides still apply*
+
+Unlike `crrweird` however, the results are 4-bit wide, so the packing
+will begin to spill over to other destination elements.  8 results per
+destination at 4-bits each still fits into destination elwidth at 32-bit,
+but for 16-bit and 8-bit obviously this does not fit, and must split
+across to the next element
+
+When for example destination elwidth is 16-bit (0b10) the following packing
+occurs:
+
+- SVRM bits 6:7 equal to 0b00 - one 4-bit result element packed into the
+  first 4-bits of the 16-bit destination element (in the first 4 LSBs)
+- SVRM bits 6:7 equal to 0b01 - two 4-bit result elements packed into the
+  first 8-bits of the 16-bit destination element (in the first 8 LSBs)
+- SVRM bits 6:7 equal to 0b10 - four 4-bit result elements packed into each
+  16-bit destination element
+- SVRM bits 6:7 equal to 0b11 - eight 4-bit result elements, the first four
+  of which are packed into the first 16-bit destination element, the
+  second four of which are packed into the second 16-bit destination element.
 
 **mtcrrweird**